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ADDRDEC LOGIC

The ADDRDEC logic decodes the current address and

generates the enable signal for the appropriate register.

The enable values for the registers and counters change

on the falling edge of LOAD. Two types of ADDRDEC logic

is enabled by 2 pair of addresses, Addresses 22 or 54

(Vectored Restart logic) and Addresses 23 or 55 (Vectored

Clear logic). Loading these addresses will enable the

appropriate logic and put the part into either a Restart (all

counter registers are reinitialized with preprogrammed

data) or Clear (all registers are cleared to zero) state.

Reloading the same ADDRDEC address will not cause any

change in the state of the part. The outputs during these

states are frozen and the internal CLOCK is disabled.

Clocking the part during a Vectored Restart or Vectored

Clear state will have no effect on the part. To resume oper-

ation in the new state, or disable the Vectored Restart or

Vectored Clear state, another non-ADDRDEC address

must be loaded. Operation will begin in the new state on

the rising edge of the non-ADDRDEC load pulse. It is rec-

ommended that an unused address be loaded following an

ADDRDEC operation to prevent data registers from acci-

dentally being corrupted. The following Addresses are

used by the device.

Address 0

Status Register REG0

Address 1–18Data Registers REG1–REG18

Address 19–21Unused

Address 22/54Restart Vector (Restarts Device)

Address 23/55Clear Vector (Zeros All Registers)

Address 24–31Unused

Address 32–50Register Scan Addresses

Address 51–53Counter Scan Addresses

Address 56–63Unused

At any given time only one register at most is selected. It is

possible to have no registers selected.

VECTORED RESTART ADDRESS

The function of addresses 22 (16H) or 54 (36H) are similar

to that of the CLR pin except that the preprogramming of

the registers is not affected. It is recommended but not

required that this address is read after the initial device

configuration load sequence. A 1 on the ADDRDATA pin

(Auto Addressing Mode) will not cause this address to

automatically increment. The address will loop back onto

itself regardless of the state of ADDRDATA unless the

address on the Data inputs has been changed with

ADDRDATA at 0.

VECTORED CLEAR ADDRESS

Addresses 23 (17H) or 55 (37H) is used to clear all regis-

ters to zero simultaneously. This function may be desirable

to use prior to loading new data into the Data or Status

Registers. This address is read into the device in a similar

fashion as all of the other registers. A 1 on the ADDRDATA

pin (Auto Addressing Mode) will not cause this address to

automatically increment. The address will loop back onto

itself regardless of the state of ADDRDATA unless the

address on the Data inputs has been changed with

ADDRDATA at 0.

FIGURE 4. ADDRDEC Timing

GEN LOCKING

The ACT715 and ACT715-R is designed for master SYNC

and BLANK signal generation. However, the devices can

be synchronized (slaved) to an external timing signal in a

limited sense. Using Vectored Restart, the user can reset

the counting sequence to a given location, the beginning,

at a given time, the rising edge of the LOAD that removes

Vector Restart. At this time the next CLOCK pulse will be

CLOCK 1 and the count will restart at the beginning of the

first odd line.

Preconditioning the part during normal operation, before

the desired synchronizing pulse, is necessary. However,

since LOAD and CLOCK are asynchronous and indepen-

dent, this is possible without interruption or data and perfor-

mance corruption. If the defaulted 14.31818 MHz RS-170

values are being used, preconditioning and restarting can

be minimized by using the CLEAR pulse instead of the

Vectored Restart operation. The ACT715-R is better suited

for this application because it eliminates the need to pro-

gram a 1 into Bit 10 of the Status Register to enable the

CLOCK. Gen Locking to another count location other than

the very beginning or separate horizontal/vertical resetting

is not possible with the ACT715 nor the ACT715-R.

SCAN MODE LOGIC

A scan mode is available in the ACT715 that allows the

user to non-destructively verify the contents of the regis-

ters. Scan mode is invoked through reading a scan

address into the address register. The scan address of a

given register is defined by the Data register address

+ 32.

The internal Clocking signal is disabled when a scan

address is read. Disabling the clock freezes the device in

it's present state. Data can then be serially scanned out of

the data registers through the ODD/EVEN Pin. The LSB

will be scanned out first. Since each register is 12 bits wide,

completely scanning out data of the addressed register will

require 12 CLOCK pulses. More than 12 CLOCK pulses on

the same register will only cause the MSB to repeat on the

output. Re-scanning the same register will require that reg-

ister to be reloaded. The value of the two horizontal

counters and 1 vertical counter can also be scanned out by

using address numbers 51–53. Note that before the part

will scan out the data, the LOAD signal must be brought

back HIGH.

Normal device operation can be resumed by loading in a

non-scan address. As the scanning of the registers is a

non-destructive scan, the device will resume correct opera-

tion from the point at which it was halted.