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74ACT818SPC Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74ACT818SPC Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Pin Descriptions Functional Description Data transfers into the diagnostic register occur on the LOW-to-HIGH transition of DCLK. Mode and SDI deter- mine what data source will be loaded. The pipeline register is loaded on the LOW-to-HIGH transition of PCLK. Mode selects whether the data source is the data input or the diagnostic register output. Because of the independence of the clock inputs, data can be shifted in the diagnostic regis- ter via DCLK and loaded into the pipeline register from the data input via PCLK simultaneously, as long as no setup or hold times are violated. This simultaneous operation is legal. Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Diagnostic Register Block Diagram Pin Names Description D0–D7 Data Inputs SDI Serial Data Input DCLK Diagnostics Clock MODE Control Input PCLK Pipeline Register Clock OEY Output Enable Input SDO Serial Data Output Y0–Y7 Data Outputs Inputs Outputs Operation SDI MODE DCLK PCLK SDO Diagnostic Reg. Pipeline Reg. XL XS7 SI <SI − 1, NA Serial Shift; D7–D0 Disabled SO <SD I XL X S7 NA PI <DI Normal Load Pipeline Register LH XL SI <YI NA Load Diagnostic Register from Y; DI Disabled XHX SDI NA PI <SI Load Pipeline Register from Diagnostic Register HH X H Hold NA Hold Diagnostic Register; DI Enabled |
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