February 1989

Revised January 1999

© 1999 Fairchild Semiconductor Corporation

DS010144.prf

www.fairchildsemi.com

74ACT2708

64 x 9 First-In, First-Out Memory

General Description

The ACT2708 is an expandable first-in, first-out memory

organized as 64 words by 9 bits. An 85 MHz shift-in and 60

MHz shift-out typical data rate makes it ideal for high-speed

applications. It uses a dual port RAM architecture with

pointer logic to achieve the high speed with negligible fall-

through time.

Separate Shift-In (SI) and Shift-Out (SO) clocks control the

use of synchronous or asynchronous write or read. Other

controls include a Master Reset (MR) and Output Enable

(OE) for initializing the internal registers and allowing the

data outputs to be 3-STATE. Input Ready (IR) and Output

Ready (OR) signal when the FIFO is ready for I/O opera-

tions. The status flags HF and FULL indicate when the

FIFO is full, empty or half full.

The FIFO can be expanded to provide different word

lengths by tying off unused data inputs.

Features

s 64-words by 9-bit dual port RAM organization

s 85 MHz shift-in, 60 MHz shift-out data rate, typical

s Expandable in word width only

s TTL-compatible inputs

s Asynchronous or synchronous operation

s Asynchronous master reset

s Outputs source/sink 8 mA

s 3-STATE outputs

s Full ESD protection

s Input and output pins directly in line for easy board lay-

out

s TRW 1030 work-alike operation

Applications

• High-speed disk or tape controllers

• A/D output buffers

• High-speed graphics pixel buffer

• Video time base correction

• Digital filtering

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignment for DIP

Pin Descriptions

FACT

™ is a trademark of Fairchild Semiconductor Corporation.

Order Number

Package Number

Package Description

74ACT2708PC

N28B

28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide

Pin Names

Description

Data Inputs

MR

Master Reset

OE

Output Enable Input

SI

Shift-In

SO

Shift-Out

IR

Input Ready

OR

Output Ready

HF

Half Full Flag

FULL

Full Flag

Data Outputs