L4B datasheet(9/42 Pages) NXP

Part #	L4B

Description	Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up and Agile I/O

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Manufacturer	NXP [NXP Semiconductors]

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PCAL9554B_PCAL9554C

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Product data sheet

Rev. 2 — 10 December 2012

9 of 42

NXP Semiconductors

PCAL9554B; PCAL9554C

Low-voltage 8-bit I2C-bus/SMBus low power I/O port

6.4.8 Pull-up/pull-down selection register (44h)

The I/O port can be configured to have pull-up or pull-down resistor by programming the

pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k

 pull-up

resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k

 pull-down resistor for that

I/O pin. If the pull-up/down feature is disconnected, writing to this register will have no

effect on I/O pin. Typical value is 100 k

 with minimum of 50 k and maximum of 150 k.

6.4.9 Interrupt mask register (45h)

Interrupt mask register is set to logic 1 upon power-on, disabling interrupts during system

start-up. Interrupts may be enabled by setting corresponding mask bits to logic 0. If an

input changes state and the corresponding bit in the Interrupt mask register is set to 1, the

interrupt is masked and the interrupt pin (INT) will not be asserted. If the corresponding bit

in the Interrupt mask register is set to 0, the interrupt pin will be asserted.

When an input changes state and the resulting interrupt is masked (interrupt mask bit is

1), setting the input mask register bit to 0 will cause the interrupt pin to be asserted. If the

interrupt mask bit of an input that is currently the source of an interrupt is set to 1, the

interrupt pin will be de-asserted.

6.4.10 Interrupt status register (46h)

This read-only register is used to identify the source of an interrupt. When read, a logic 1

indicates that the corresponding input pin was the source of the interrupt. A logic 0

indicates that the input pin is not the source of an interrupt.

When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt

status bit will return logic 0.

Table 14.

Pull-up/pull-down selection register (address 44h)

Bit

7

6

5

4

3

2

1

0

Symbol

PUD7

PUD6

PUD5

PUD4

PUD3

PUD2

PUD1

PUD0

Default

11

Table 15.

Interrupt mask register (address 45h)

Bit

7

6

5

4

3

2

1

0

Symbol

M7

M6

M5

M4

M3

M2

M1

M0

Default

11

Table 16.

Interrupt status register (address 46h)

Bit

7

6

5

4

3

2

1

0

Symbol

S7

S6

S5

S4

S3

S2

S1

S0

Default

00

Similar Description - L4B

Manufacturer	Part #	Datasheet	Description
NXP Semiconductors	PCA9554B	2Mb / 36P	Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up Rev. 1-19 September 2012
	PCAL9555A	2Mb / 46P	Low-voltage 16-bit I2C-bus GPIO with Agile I/O, interrupt and weak pull-up Rev. 1-3 October 2012
	PCAL9538A	2Mb / 43P	Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, reset and Agile I/O Rev. 2-10 December 2012
	PCA9555A	2Mb / 39P	Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up Rev. 1-11 September 2012
	PCAL9535A	2Mb / 46P	Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O Rev. 1-28 September 2012
	PCA9534	163Kb / 25P	8-bit I2C-bus and SMBus low power I/O port with interrupt Rev. 03-6 November 2006
	PCA9554PW-T	590Kb / 35P	8-bit I2C-bus and SMBus I/O port with interrupt Rev. 9-19 March 2013
	PCA9554D,112	590Kb / 35P	8-bit I2C-bus and SMBus I/O port with interrupt Rev. 9-19 March 2013
	PCA9554	187Kb / 30P	8-bit I2C-bus and SMBus I/O port with interrupt Rev. 07-13 November 2006
	PCA9534	146Kb / 17P	8-bit I2C and SMBus, low power I/O port with interrupt 2004 Sep 30

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