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L4B Datasheet(PDF) 9 Page - NXP Semiconductors |
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L4B Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 42 page PCAL9554B_PCAL9554C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 2 — 10 December 2012 9 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port 6.4.8 Pull-up/pull-down selection register (44h) The I/O port can be configured to have pull-up or pull-down resistor by programming the pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k pull-up resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that I/O pin. If the pull-up/down feature is disconnected, writing to this register will have no effect on I/O pin. Typical value is 100 k with minimum of 50 k and maximum of 150 k. 6.4.9 Interrupt mask register (45h) Interrupt mask register is set to logic 1 upon power-on, disabling interrupts during system start-up. Interrupts may be enabled by setting corresponding mask bits to logic 0. If an input changes state and the corresponding bit in the Interrupt mask register is set to 1, the interrupt is masked and the interrupt pin (INT) will not be asserted. If the corresponding bit in the Interrupt mask register is set to 0, the interrupt pin will be asserted. When an input changes state and the resulting interrupt is masked (interrupt mask bit is 1), setting the input mask register bit to 0 will cause the interrupt pin to be asserted. If the interrupt mask bit of an input that is currently the source of an interrupt is set to 1, the interrupt pin will be de-asserted. 6.4.10 Interrupt status register (46h) This read-only register is used to identify the source of an interrupt. When read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input pin is not the source of an interrupt. When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit will return logic 0. Table 14. Pull-up/pull-down selection register (address 44h) Bit 7 6 5 4 3 2 1 0 Symbol PUD7 PUD6 PUD5 PUD4 PUD3 PUD2 PUD1 PUD0 Default 11 11 11 11 Table 15. Interrupt mask register (address 45h) Bit 7 6 5 4 3 2 1 0 Symbol M7 M6 M5 M4 M3 M2 M1 M0 Default 11 11 11 11 Table 16. Interrupt status register (address 46h) Bit 7 6 5 4 3 2 1 0 Symbol S7 S6 S5 S4 S3 S2 S1 S0 Default 00 00 00 00 |
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