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PCAL9554CPW Datasheet(PDF) 5 Page - NXP Semiconductors |
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PCAL9554CPW Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 42 page PCAL9554B_PCAL9554C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 2 — 10 December 2012 5 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port 6. Functional description Refer to Figure 1 “Block diagram of PCAL9554B/PCAL9554C”. 6.1 Device address A2, A1 and A0 are the hardware address package pins and are held to either HIGH (logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH (logic 1) selects a read operation, while a LOW (logic 0) selects a write operation. 6.2 Pointer register and command byte Following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the Pointer register in the PCAL9554B/PCAL9554C. Two bits of this data byte state the operation (read or write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that will be affected. Bit 6 in conjunction with the lower three bits of the Command byte are used to point to the extended features of the device (Agile I/O). This register is write only. a. PCAL9554B address b. PCAL9554C address Fig 4. Device address R/W 002aah207 0 1 0 0 A2 A1 A0 slave address fixed hardware selectable R/W 002aah208 0 1 1 1 A2 A1 A0 slave address fixed hardware selectable Fig 5. Pointer register bits 002aaf540 B7 B6 B5 B4 B3 B2 B1 B0 |
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