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74ABT652CMTC Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74ABT652CMTC Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 10 page November 1992 Revised January 1999 © 1999 Fairchild Semiconductor Corporation DS011512.prf www.fairchildsemi.com 74ABT652 Octal Transceivers and Registers with 3-STATE Outputs General Description The ABT652 consists of bus transceiver circuits with D- type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are pro- vided to control the transceiver function. Features s Independent registers for A and B buses s Multiplexed real-time and stored data s A and B output sink capability of 64 mA, source capability of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignment for SOIC, SSOP and TSSOP Pin Descriptions Order Number Package Number Package Description 74ABT652CSC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ABT652CMSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT652CMTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Description A0–A7 Data Register A Inputs/3-STATE Outputs B0–B7 Data Register B Inputs/3-STATE Outputs CPAB, CPBA Clock Pulse Inputs SAB, SBA Select Inputs OEAB, OEBA Output Enable Inputs |
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