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## MMSF10N02Z Datasheet(PDF) 4 Page - Motorola, Inc

 Part No. MMSF10N02Z Description SINGLE TMOS POWER MOSFET 10 AMPERES 20 VOLTS Download 10 Pages Scroll/Zoom 100% Manufacturer MOTOROLA [Motorola, Inc] Direct Link http://www.freescale.com Logo

## MMSF10N02Z Datasheet(HTML) 4 Page - Motorola, Inc

 4 / 10 pageMMSF10N02Z4Motorola TMOS Power MOSFET Transistor Device DataPOWER MOSFET SWITCHINGSwitching behavior is most easily modeled and predictedby recognizing that the power MOSFET is charge controlled.The lengths of various switching intervals (∆t) are deter-mined by how fast the FET input capacitance can be chargedby current from the generator.The published capacitance data is difficult to use for calculat-ing rise and fall because drain–gate capacitance variesgreatly with applied voltage. Accordingly, gate charge data isused. In most cases, a satisfactory estimate of average inputcurrent (IG(AV)) can be made from a rudimentary analysis ofthe drive circuit so thatt = Q/IG(AV)During the rise and fall time interval when switching a resis-tive load, VGS remains virtually constant at a level known asthe plateau voltage, VSGP. Therefore, rise and fall times maybe approximated by the following:tr = Q2 x RG/(VGG – VGSP)tf = Q2 x RG/VGSPwhereVGG = the gate drive voltage, which varies from zero to VGGRG = the gate drive resistanceand Q2 and VGSP are read from the gate charge curve.During the turn–on and turn–off delay times, gate current isnot constant. The simplest calculation uses appropriate val-ues from the capacitance curves in a standard equation forvoltage change in an RC network. The equations are:td(on) = RG Ciss In [VGG/(VGG – VGSP)]td(off) = RG Ciss In (VGG/VGSP)The capacitance (Ciss) is read from the capacitance curve ata voltage corresponding to the off–state condition when cal-culating td(on) and is read at a voltage corresponding to theon–state when calculating td(off).At high switching speeds, parasitic circuit elements com-plicate the analysis. The inductance of the MOSFET sourcelead, inside the package and in the circuit wiring which iscommon to both the drain and gate current paths, produces avoltage at the source which reduces the gate drive current.The voltage is determined by Ldi/dt, but since di/dt is a func-tion of drain current, the mathematical solution is complex.The MOSFET output capacitance also complicates themathematics. And finally, MOSFETs have finite internal gateresistance which effectively adds to the resistance of thedriving source, but the internal resistance is difficult to mea-sure and, consequently, is not specified.The resistive switching time variation versus gate resis-tance (Figure 9) shows how typical switching performance isaffected by the parasitic circuit elements. If the parasiticswere not present, the slope of the curves would maintain avalue of unity regardless of the switching speed. The circuitused to obtain the data is constructed to minimize commoninductance in the drain and gate circuit loops and is believedreadily achievable with board mounted components. Mostpower electronic loads are inductive; the data in the figure istaken with a resistive load, which approximates an optimallysnubbed inductive load. Power MOSFETs may be safely op-erated into an inductive load; however, snubbing reducesswitching losses.Figure 7. Capacitance VariationVDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)0812TJ = 25°CVGS = 0 V15001000500016CissCossCrss420002061014218

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