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74ABT16952 Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74ABT16952 Datasheet(HTML) 1 Page - Fairchild Semiconductor |
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© 2001 Fairchild Semiconductor Corporation DS011647 www.fairchildsemi.com November 1993 Revised August 2001 74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs General Description The ABT16952 is a 16-bit registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-STATE output enable signals are provided for each register. The output pins are guaranteed to source 32 mA and to sink 64 mA. Features s Separate clock, clock enable and 3-STATE output enable provided for each register s A and B output sink capability of 64 mA source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability Ordering Code: Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code. Pin Descriptions Output Control Register Function Table (Applies to A or B Register) H = HIGH Voltage Level Z = HIGH Impedance L = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial NC = No Change Connection Diagram Order Number Package Number Package Description 74ABT16952CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74ABT16952CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pin Names Description A0–A15 Data Register A Inputs/ B-Register 3-STATE Outputs B0–B15 Data Register B Inputs/ A-Register 3-STATE Outputs CPABn, CPBAn Clock Pulse Inputs CEAn, CEBn Clock Enable OEABn, OEBAn Output Enable Inputs OE Internal Q Output Function H X Z Disable Outputs L L L Enable Outputs LH H Inputs Internal Function DCP CE Q X X H NC Hold Data L L L Load Data H L H |
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