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T8535B Datasheet(PDF) 34 Page - Agere Systems |
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T8535B Datasheet(HTML) 34 Page - Agere Systems |
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34 / 50 page  34 Agere Systems Inc. Preliminary Data Sheet September 2001 T8535B/T8536B Quad Programmable Codec Timing Characteristics Control Interface Timing Serial Control Port Timing Table 17. Serial Control Port Timing (See Figures 22 and 23.) *The tSXBDLY delay is from either DCLK or CS, whichever transition is later, for the first bit of the byte. Symbol Parameter Test Conditions Min Typ Max Unit fDCLK Clock Frequency (all commands) — — — 4096 kHz tCSSETUP Chip Select Setup Time, Normal Mode DCLK = 4.096 MHz 7 — — ns tCSHOLD Chip Select Hold Time, Normal Mode DCLK = 4.096 MHz 4 — — ns tSXDLY Output Data Delay, Normal Mode DCLK = 4.096 MHz — — 9 ns tSDHOLD Input Data Hold Time, Normal Mode DCLK = 4.096 MHz 4 — — ns tSDSETUP Input Data Setup Time, Normal Mode DCLK = 4.096 MHz 7 — — ns tSDZ Output Data, High Impedance DCLK = 4.096 MHz 100 — — ns tRISE Clock Edge Rise Time DCLK = 4.096 MHz — — 12 ns tFALL Clock Edge Fall Time DCLK = 4.096 MHz — — 12 ns tRISE, tFALL Line Driver Rise/Fall Time (DO output) IL = 15 mA, CLOAD = 100 pF — — 30 ns tCSBHOLD Chip Select Hold Time, Byte-by-Byte Mode DCLK = 4.096 MHz 4 — — ns tSXBDLY Output Data Delay, Byte-by-Byte Mode DCLK = 4.096 MHz* — — 9 ns tCSBSETUP Chip Select Setup Time, Byte-by-Byte Mode DCLK = 4.096 MHz 7 — — ns tSDBHOLD Data Hold Time, Byte-by-Byte Mode DCLK = 4.096 MHz 4 — — ns tSDBSETUP Data Setup Time, Byte-by-Byte Mode DCLK = 4.096 MHz 7 — — ns |
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