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T8535B Datasheet(PDF) 25 Page - Agere Systems

Part No. T8535B
Description  T8535B/T8536B Quad Programmable Codec
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Maker  AGERE [Agere Systems]
Homepage  http://www.agere.com
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T8535B Datasheet(HTML) 25 Page - Agere Systems

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Agere Systems Inc.
25
Preliminary Data Sheet
September 2001
T8535B/T8536B Quad Programmable Codec
Functional Description (continued)
SLIC Control Capabilities (continued)
The fast scan mode allows for a minimal data transfer
on the serial bus to monitor bits 0 and 1 of the SLIC
data memory location (159). If these two bits are wired
as inputs to the off-hook and/or ring ground detection
circuits, a convenient method of rapidly scanning for
these two functions is obtained. Bits 2 and 3 default to
outputs; thus, they are convenient to provide control of
the SLIC state. In any event, all six leads are program-
mable for maximum flexibility.
Suggested Initialization Procedures
It is suggested that upon powerup, a hardware reset be
used to set the device into a known state. The serial
interface should then be used to load the memory
addresses that differ from the default values (the write
all channels command is convenient for this function). If
other devices are controlled by the SLIC data memory
location, then it also should be loaded with a known
configuration. After the completion of this sequence,
the device is ready to be activated. Depending on the
application, the next step may either be normal opera-
tion or a set of test sequences. After the initialization of
the memory, the device and associated line card
devices can be controlled by using memory locations
130, 131, 145, 155, 156, 157, 158, 159, and 129; that
is, by supplying the PCM bus time-slot addresses,
switching the SLIC into the proper mode, and activat-
ing the codec. Within memory location 129, the codec
would normally be placed into active mode, with both
directions of the PCM bus enabled at the start of a call.
At the completion of a call, the codec should be placed
into standby mode and the PCM bus disabled. Great
caution should be used when changing the memory
while the codec is in active mode, since termination
impedances, balance impedances, and gains may
change. These changes are likely to yield undesirable
system effects. It is safe to refresh coefficients that are
known to be unchanging in the application. It is always
possible to read the memory to verify its contents with-
out deleterious effects on codec operation. Normal
operation would load the memory and perform all gain
adjustments while the codec is in standby mode.
Under no circumstances should memory above
address 162 be written, since this section of memory is
used for state data and intermediate results. Also, all
reserved addresses should not be written. Changing
this information may have deleterious effects on sys-
tem operation.
Signal Processing
Figure 21 details the signal processing functional
blocks of one channel of the codec.
0497F
* Programmable blocks.
Figure 21. Internal Signal Processing
SPEED
FROM
PCM
BUS
*
GRX1
GAIN
8 kHz
COMP
TO LIN.
TRANSFER
XLPF
GAIN
TWEAKING
GRX2
SINC3
∑-∆
D/A
1-bit
D/A
RCF
SMF
TO
0 dB
BAL
*
32 kHz
4096 kHz
LPF
*
DIGITAL
SLIC
TO
PCM
BUS
*
GAIN
GTX2
LIN.TO
COMP
YLPF
*
GAIN
TWEAKING
GTX1
SINC3
*
FROM
0 dB TO 24 dB
SLIC
TRANSFER
TEQ
∑-∆
A/D
LPF
RTZ
8 STEPS
IN 5 STEPS
XAG
ANALOG
CTZ
*


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