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T8535B Datasheet(PDF) 13 Page - Agere Systems

Part No. T8535B
Description  T8535B/T8536B Quad Programmable Codec
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Maker  AGERE [Agere Systems]
Homepage  http://www.agere.com

T8535B Datasheet(HTML) 13 Page - Agere Systems

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Agere Systems Inc.
Preliminary Data Sheet
September 2001
T8535B/T8536B Quad Programmable Codec
Functional Description
Clocking Considerations
The PCM bus uses BCLK as the bit clock and the one-
going edge of FS to determine the location of the
beginning of a frame. These two clocks must be
derived from the same source. Internally, the device
develops all the internal clocks with a phase-locked
loop that uses BCLK as the timing source. BCLK and
FS must be continuously present and without gaps in
order for the device to operate correctly.
DCLK is used to clock the internal serial interface and
may be asynchronous to the other clocks. There is no
need to derive this clock from the same source as the
other clocks. The serial bus may be operated at any
speed up to 4.096 Mbits/s. DCLK can be gapped.
There is no limit on the number of devices on the same
serial bus.
The Control Interface
The device is controlled via a series of memory loca-
tions accessed by a serial data connection to the exter-
nal master controller. This interface operates using the
chip select lead to enable transmission of information.
All chip functions are enabled or disabled by setting or
clearing bits in the control memory. Filter coefficients
and gain adjustments are also stored in this memory.
The codec has both a serial input lead and a serial out-
put lead. These may be used individually for a 4-wire
serial interface, or tied together for a 2-wire interface.
The line driver circuitry is capable of driving relatively
high currents so that in the event that the line is long
enough to show significant transmission line effects, it
can be terminated in the characteristic impedance at
each end with resistors to VCC and ground.
All data transfers on the serial bus are byte oriented
with the least significant bit (shown in this data sheet as
bit 0) transmitted first, followed by the more significant
bits. For data fields, the least significant byte of the first
data byte is transmitted first, followed by the more sig-
nificant bytes, each byte transmitted LSB first. This for-
mat is compatible with the serial port on most
There are two different modes of operation for the
serial interface: the normal mode and the byte-by-byte
mode. These two modes differ in the data clocking and
the manner in which CS is used to control the transfer.
Note that the CS lead is used to control the transfer of
serial data from master controller to slave codec and in
the reverse direction.
In normal mode (INTS pin open), the CS lead must go
low for the duration of the transfer. CS is latched by
DCLK on a positive-going clock edge. DI is latched by
DCLK on a negative-going clock edge. DCLK may be
continuous, but only needs to be present to clock data
when CS is low (gapped clock). When using gapped
clock, DCLK can remain high or low when CS is high.
The only error check performed by the codec is to
verify that CS is low for an integral number of bytes.
Detection of an active chip select for other than an
integral multiple of 8 bits results in the operation being
terminated. The next active excursion of chip select will
be interpreted as a new command; hence, the serial
I/O interface can always be initialized by asserting CS
for a number of clock periods that is not an integral
multiple of 8. CS is captured using DCLK, so DCLK
must be transitioned to perform this initialization.
The byte-by-byte mode (INTS pin tied to ground) uses
CS to control each byte of the transfer. In this mode,
CS goes low for exactly 8 bits at a time, corresponding
to a 1-byte transfer either to or from the codec chip.
DCLK can be continuous or gapped. When using a
gapped clock, DCLK can remain high or low when CS
is high. CS and DI are latched on a positive-going clock
edge. Repeated transitions of CS are used to control
subsequent bytes of data to/from the codec. For a write
command in this mode, CS must go low for each byte
of the transfer until the transfer is complete. For a read
command, CS will go low for each of the 3 bytes of the
read command transferred to the device, then low
again for each byte to be read. Notice that the total
number of bytes transferred (and excursions on CS) is
N + 3, where N is the number of bytes to be read in the
command. This mode of operation is useful in cases
where the master is a microprocessor with a built-in
UART that transfers 1 byte at a time. Error detection is
limited to detection of an active CS for other than an
integral multiple of 8 bits. Recovery is the same as nor-
mal mode.
Flow control can be accomplished by suspending the
transitions on DCLK by holding either state. During the
data transfer, CS must remain low while clock transi-
tions are suspended with DCLK in either state.

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