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OR3T80 Datasheet(PDF) 33 Page - Agere Systems |
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OR3T80 Datasheet(HTML) 33 Page - Agere Systems |
33 / 210 page Lucent Technologies Inc. 33 Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) xL Routing Lines. The xL routing lines run vertically and horizontally the height and width of the array, respectively. There are a total of 20 xL routing lines per PLC: ten horizontal (hxL[9:0]) and ten vertical (vxL[9:0]). Each of the xL lines connects to the PIC routing at either end. The xL lines are intended prima- rily for global signals that must travel long distances and require minimum delay and/or skew, such as clocks or 3-state buses. Each xL line (also called a long line) drives a buffer in each PLC that can drive onto the horizontal and verti- cal local clock routing segments (lCLK) in the PLC. Also, two out of each group of ten xL segments in each PLC can be driven by a buffer attached to a clock spine (described later) allowing local distribution of global clock signals. More general-purpose connections to the long lines can be made through the xBID segments in a PLC. Each long line is connected to an xBID segment on a bit-by-bit basis. These BIDI connections allow cor- ner turning from horizontal to vertical long lines, and connection between long lines and x1 or x5 segments. xH Routing Segments. Ten by-half (xH) routing seg- ments run horizontally (hxH[9:0]) and ten xH routing segments run vertically (vxH[9:0]) in each row and col- umn in the array. These routing segments travel a dis- tance of one-half the PLC array before being broken in the middle of the array in the interquad area (discussed later). They also connect at the periphery of the FPGA to the PICs, like the xL lines. xH routing segments con- nect to the PLCs only by switching segments. They are intended for fast signal interconnect. Clock (and Global CE and LSR) Routing Segments. For a very fast and low-skew clock (or other global sig- nal tree), clock routing segments run the entire height and width of the PLC array. There are two clock routing segments per PLC: one horizontal (hCLK) and one ver- tical (vCLK). The source for these clock routing seg- ments can be any of the I/O buffers in the PIC, the Series 3 ExpressCLK inputs, user logic, or the pro- grammable clock manager (PCM). The horizontal clock routing segments (hCLK) are alternately driven by the left and right PICs. The vertical clock routing segments (vCLK) are alternately driven by the top and bottom PICs. The clock routing segments are designed to be a clock spine. In each PLC, there is a fast connection available from the clock segment to a long-line driver (described earlier). With this connection, one of the clock routing segments in each PLC can be used to drive one of the ten xL routing segments perpendicular to it, which, in turn, creates a clock spine tree. This feature is dis- cussed in detail in the Clock Distribution Network sec- tion. Special connectivity is provided in each PLC to connect the clock enable signals (CE and ASWE) and the LSR signal to the clock network for fast global control signal distribution. CE and ASWE have a special connection to the horizontal clock spine, and LSR has a special connection to the vertical clock spine. This allows both signals to be routed globally within the same PLC, if desired; however, this will consume some of the resources available for clock signal routing. If using these spines, the clock enable signal must come from the right or left edge of the device, and the LSR signal must come from the top or bottom of the device due to their horizontal and vertical connectivity, respectively, to the clock network. Minimizing Routing Delay The CIP is an active element used to connect two rout- ing segments. As an active element, it adds signifi- cantly to the resistance and capacitance of a routing network (net), thus increasing the net’s delay. The advantage of the x1 segment over an x5 segment is routing flexibility. A net from one PLC to the next is eas- ily routed by using x1 routing segments. As more CIPs are added to a net, the delay increases. To increase speed, routes that are greater than two PLCs away are routed on the x5 routing segments because a CIP is located only in every fifth PLC. A net that spans eight PLCs requires seven x1 routing segments and six CIPs. Using x5 routing segments, the same net uses two routing segments and one CIP. |
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