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OR3T80 Datasheet(PDF) 98 Page - Agere Systems |
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OR3T80 Datasheet(HTML) 98 Page - Agere Systems |
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98 / 210 page  98 98 Lucent Technologies Inc. Data Sheet June 1999 ORCA Series 3C and 3T FPGAs FPGA Configuration Modes (continued) Daisy-Chaining Multiple FPGAs can be configured by using a daisy- chain of the FPGAs. Daisy-chaining uses a lead FPGA and one or more FPGAs configured in slave serial mode. The lead FPGA can be configured in any mode except slave parallel mode. (Daisy-chaining is available with the boundary-scan ram_w instruction discussed later.) All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on positive CCLK and out on negative CCLK edges. An upstream FPGA that has received the preamble and length count outputs a high on DOUT until it has received the appropriate number of data frames so that downstream FPGAs do not receive frame start bit pairs. After loading and retransmitting the preamble and length count to a daisy-chain of slave devices, the lead device loads its configuration data frames. The loading of configuration data continues after the lead device has received its configuration data if its internal frame bit counter has not reached the length count. When the configuration RAM is full and the num- ber of bits received is less than the length count field, the FPGA shifts any additional data out on DOUT. The configuration data is read into DIN of slave devices on the positive edge of CCLK, and shifted out DOUT on the negative edge of CCLK. Figure 63 shows the connections for loading multiple FPGAs in a daisy- chain configuration. The generation of CCLK for the daisy-chained devices that are in slave serial mode differs depending on the configuration mode of the lead device. A master paral- lel mode device uses its internal timing generator to produce an internal CCLK at eight times its memory address rate (RCLK). The asynchronous peripheral mode device outputs eight CCLKs for each write cycle. If the lead device is configured in slave mode, CCLK must be routed to the lead device and to all of the daisy-chained devices. 5-4488(F Figure 63. Daisy-Chain Configuration Schematic As seen in Figure 63, the INIT pins for all of the FPGAs are connected together. This is required to guarantee that powerup and initialization will work correctly. In general, the DONE pins for all of the FPGAs are also connected together as shown to guarantee that all of the FPGAs enter the start-up state simultaneously. This may not be required, depending upon the start-up sequence desired. VDD EPROM PROGRAM D[7:0] OE CE A[17:0] A[17:0] D[7:0] DONE M2 M1 M0 DONE HDC LDC RCLK CCLK DOUT DIN DOUT DIN CCLK DONE DOUT INIT INIT INIT CCLK VDD VDD OR GND PRGM PRGM M2 M1 M0 PRGM M2 M1 M0 VDD VDD HDC LDC RCLK HDC LDC RCLK VDD ORCA SERIES FPGA SLAVE #2 ORCA SERIES FPGA MASTER ORCA SERIES FPGA SLAVE #1 |
Similar Part No. - OR3T80 |
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Similar Description - OR3T80 |
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