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OR3T80 Datasheet(PDF) 81 Page - Agere Systems |
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OR3T80 Datasheet(HTML) 81 Page - Agere Systems |
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81 / 210 page  Lucent Technologies Inc. 81 Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) Table 31. PCM Control Registers (continued) Bit # Function Register 4—DLL 1x Duty-Cycle Programming Bits [2:0] Duty-Cycle/Delay Selection for Duty Cycle/Delays Less Than or Equal to 50%. The duty- cycle/delay is (value of bits [7:6]) * 25% + ((value of bits [2:0]) + 1) * 3.125%. See the description for bits [7:6]. Bits [5:3] Duty-Cycle/Delay Selection for Duty Cycle/Delays Greater Than 50%. The duty-cycle/delay is (value of bits [7:6]) * 25% + ((value of bits [5:3]) + 1) * 3.125%. See the description for bits [7:6]. Bits [7:6] Master Duty Cycle Control: 00: duty cycle 3.125% to 25% 01: duty cycle 28.125% to 50% 10: duty cycle 53.125% to 75% 11: duty cycle 78.125% to 96.875% Example: A 40.625% duty cycle, bits [7:0] are 01 XXX 100, where X is a don’t care because the duty cycle is not greater than 50%. Example: The PCM output clock should be delayed 96.875% (31/32) of the input clock period. Bits [7:0] are 11110XXX, which is 78.125% from bits [7:6] and 18.75% from bits [5:3]. Bits [2:0] are don’t care (X) because the delay is greater than 50%. Register 5—Mode Programming Bit 0 DLL/PLL Mode Selection Bit. 0 = DLL, 1 = PLL. Default is DLL mode. Bit 1 Reserved. Bit 2 PLL Phase Detector Feedback Input Selection Bit. 0 = feedback signal from routing/ ExpressCLK , 1 = feedback from programmable delay line output. Default is 0. Has no effect in DLL mode. Bit 3 Reserved. Bit 4 1x/2x Clock Selection Bit for DLL Mode. 0 = 1x clock output, 1 = 2x clock output. Default is 1x clock output. Has no effect in PLL mode. Bits [7:5] Reserved. |
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