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ORT4622 Datasheet(PDF) 38 Page - Agere Systems |
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ORT4622 Datasheet(HTML) 38 Page - Agere Systems |
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38 / 90 page  38 38 Lucent Technologies Inc. ORCA ORT4622 FPSC Preliminary Data Sheet Four-Channel x 622 Mbits/s Backplane Transceiver March 2000 Lucent Technologies Inc. FPGA Configuration Data Format (continued) Bit Stream Error Checking There are three different types of bit stream error checking performed in the ORCA Series 3+ FPSCs: ID frame, frame alignment, and CRC checking. The ID data frame is sent to a dedicated location in the FPSC. This ID frame contains a unique code for the device for which it was generated. This device code is compared to the internal code of the FPSC. Any differ- ences are flagged as an ID error. This frame is auto- matically created by the bit stream generation program in ORCA Foundry. Each data and address frame in the FPSC begins with a frame start pair of bits and ends with eight stop bits set to 1. If any of the previous stop bits were a 0 when a frame start pair is encountered, it is flagged as a frame alignment error. Error checking is also done on the FPSC for each frame by means of a checksum byte. If an error is found on evaluation of the checksum byte, then a checksum/parity error is flagged. When any of the three possible errors occur, the FPSC is forced into an idle state, forcing INIT low. The FPSC will remain in this state until either the RESET or PRGM pins are asserted. If using either of the MPI modes to configure the FPSC, the specific type of bit stream error is written to one of the MPI registers by the FPGA configuration logic. The PGRM bit of the MPI control register can also be used to reset out of the error condition and restart configura- tion. FPGA Configuration Modes There are eight methods for configuring the FPSC. Six of the configuration modes are selected on the M0, M1, and M2 input and are shown in Table 12. A fourth input, M3, is used to select the frequency of the internal oscil- lator, which is the source for CCLK in some configura- tion modes. The nominal frequencies of the internal oscillator are 1.25 MHz and 10 MHz. The 1.25 MHz fre- quency is selected when the M3 input is unconnected or driven to a high state. Note that the Master parallel mode of configuration that is available in the ORCA Series 3 FPGAs is not avail- able in the ORT4622. More information on the general FPGA modes of con- figuration can be found in the ORCA Series 3 data sheet. Table 12. Configuration Modes * Motorola is a registered trademark of Motorola, Inc. † Intel is a registered trademark of Intel Corporation. M2 M1 M0 CCLK Configuration Mode Data 0 0 0 Output Master Serial Serial 0 0 1 Input Slave Parallel Parallel 0 1 0 Output Microprocessor: Motorola* Pow- erPC Parallel 0 1 1 Output Microprocessor: Intel † i960 Parallel 100 Reserved 1 0 1 Output Async Peripheral Parallel 110 Reserved 1 1 1 Input Slave Serial Serial |
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