Electronic Components Datasheet Search |
|
ORT4622 Datasheet(PDF) 35 Page - Agere Systems |
|
ORT4622 Datasheet(HTML) 35 Page - Agere Systems |
35 / 90 page Lucent Technologies Inc. 35 Preliminary Data Sheet ORCA ORT4622 FPSC March 2000 Four-Channel x 622 Mbits/s Backplane Transceiver Lucent Technologies Inc. Memory Map (continued) Table 10. Memory Map Bit Descriptions * The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before trying to initiate a second A1/A2 corruption. † The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before trying to initiate a second B1 corruption. Powerup Sequencing for ORT4622 Device ORCA Series ORT4622 device uses two power supplies: one to power the device I/Os and the ASIC core (VDD), which is set to 3.3 V for 3.3 V operation and 5 V tolerance on input pins, and another supply for the internal FPGA logic (VDD2), which is set to 2.5 V. It is understood that many users will derive the 2.5 V core logic supply from a 3.3 V power supply, so the following recommendations are made for the powerup sequence of the supplies and allow- able delays between power supplies reaching stable voltages. In general, both the 3.3 V and the 2.5 V supplies should ramp-up and become stable as close together in time as possible. There is no delay requirement if the VDD2 (2.5 V) supply becomes stable prior to the VDD (3.3 V) supply. There is a delay requirement imposed if the VDD supply becomes stable prior to the VDD2 supply. The requirement is that the VDD2 (2.5 V) supply transition from 0 V to 2.3 V within 15.7 ms if the VDD (3.3 V) supply is already stable at a minimum of 3.0 V. If the VDD supply has not yet reached 3.0 V when the VDD2 supply has reached 2.3 V, then the requirement is that the VDD2 supply reach a minimum of 2.3 V within 15.7 ms of when the VDD supply reaches 3.0 V. If the chosen power supplies can- not meet this delay requirement, it is always possible to hold off configuration of the FPGA by asserting INIT or PRGM until the VDD2 supply has reached 2.3 V. This process eliminates any power supply sequencing issues. Bit/Register Name(s ) Bit/ Register Location (hex) Register Type Default Value (hex) Description Channel Register Block (Channel A, Channel B, Channel C, Channel D) (continued) ES overflow flags 12, 9, 6, 3 ES overflow flags 11, 8, 5, 2, 10, 7, 4, 1 enable/mask register 12, 9, 6, 3 enable/mask register 11, 8, 5, 2, 10, 7, 4, 1 2e, 46, 5e, 76 [7:0] 2f, 47, 5f, 77 [3:0] 30, 48, 60, 78 [7:0] 31, 49, 61, 79 [7:0] —4’h0 8’h00 4’h0 8’h00 These are the elastic store overflow alarm flags. LVDS link B1 parity error counter 32, 4a, 62, 7a [7:0] counter 8’h00 7-bit count + overflow-reset on read. LOF counter 33, 4b, 63, 7b [7:0] counter 8’h00 7-bit count + overflow-reset on read. A1/A2 frame error counter 34, 4c, 64, 7c [7:0] counter 8’h00 7-bit count + overflow-reset on read. |
Similar Part No. - ORT4622 |
|
Similar Description - ORT4622 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |