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OR3C55 Datasheet(PDF) 65 Page - Agere Systems |
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OR3C55 Datasheet(HTML) 65 Page - Agere Systems |
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65 / 210 page  Lucent Technologies Inc. 65 Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) (continued) PowerPC System In Figure 43, the ORCA FPGA is a memory-mapped peripheral to the PowerPC processor. The PowerPC interface uses separate address and data buses and has several control lines. The ORCA chip select lines, CS0 and CS1, are each connected to an address line coming from the PowerPC. In this manner, the FPGA is capable of a transaction with the PowerPC whenever the address line connected to CS0 is low, the address line for CS1 is high, and there is a valid address on PowerPC address lines A[27:31]. Other forms of selec- tion are possible by using the FPGA chip selects in a different way. For example, PowerPC address bits A[0:26] could be decoded to select CS0 and CS1, or if the FPGA is the only peripheral to the PowerPC, CS0 and CS1 could be tied low and high, respectively, to cause them to always be selected. If the MPI is not used for FPGA configuration, decoding logic can be implemented internal or external to the FPGA. If logic internal to the FPGA is used, the chip selects must be routed out on an output pin and then connected exter- nally to CS0 and/or CS1. If the MPI is to be used for configuration, any decode logic used must be imple- mented external to the FPGA since the FPGA logic has not been configured yet. 5-5761(F) Note: FPGA shown as a memory-mapped peripheral using CS0 and CS1. Other decoding schemes are possible using CS0 and/or CS1. Figure 43. PowerPC/MPI The basic flow of a transaction on the PowerPC/MPI interface is given below. Pin descriptions are shown in Table 16 and timing is shown in the Timing Characteris- tics section of this data sheet. For both read and write transactions, the address, chip select, and read/write (read high, write low) signals are set up at the FPGA pins by the PowerPC. The PowerPC then asserts its transfer start signal (TS) low. Data is available to the MPI during a write at the rising clock edge after the clock cycle during which TS is low. The transfer is acknowledged to the PowerPC by the low asser tion of the TA signal. The MPI PowerPC interface does not support burst transfers, so the burst inhibit signal, BI, is also asserted low during the transferacknowledge . The same process applies to a read from the MPI except that the read data is expected at the FPGA data pins by the PowerPC at the rising edge of the clock when TA is low. The MPI only drives TA low for one clock cycle. Interrupt requests can be sent to the PowerPC asyn- chronously to the read/write process. Interrupt requests are sourced by the user-logic in the FPGA. The MPI will assert the request to the PowerPC as a direct interrupt signal and/or a pollable bit in the MPI status register (discussed in the MPI Setup and Control section). The MPI will continue to assert the interrupt request until the user-logic deasserts its interrupt request signal. Table 16. PowerPC/MPI Configuration DOUT CCLK D[7:0] A[4:0] MPI_CLK MPI_RW MPI_ACK MPI_BI MPI_IRQ MPI_STRB CS0 CS1 HDC LDC D[7:0] A[27:31] CLKOUT RD/WR TA BI IRQx TS A26 A25 TO DAISY- CHAINED DEVICES POWERPC ORCA 8 FPGA SERIES 3 DONE INIT PowerPC Signal ORCA Pin Name MPI I/O Function D[0:7] D[7:0] I/O 8-bit data bus A[27:31] A[4:0] I 5-bit MPI address bus TS RD/MPI_STRB I Transfer start signal — CS0 I Active-low MPI select — CS1 I Active-high MPI select CLKOUT A7/MPI_CLK I PowerPC interface clock RD/WR A8/MPI_RW I Read (high)/write (low) signal TA A9/MPI_ACK O Active-low transfer acknowledge signal BI A10/MPI_BI O Active-low burst transfer inhibit signal Any of IRQ [7:0] A11/MPI_IRQ O Active-low interrupt request signal |
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