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OR3C55 Datasheet(PDF) 28 Page - Agere Systems |
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OR3C55 Datasheet(HTML) 28 Page - Agere Systems |
28 / 210 page 28 Lucent Technologies Inc. Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) General Routing Structure Routing resources in Series 3 FPGAs generally consist of routing segments in groups of ten, with varying lengths and connectivity to logic and other routing resources. The varying lengths of routing segments provides a hierarchy of routing capability from chip-length routes to routes within a PLC. The hierarchical nature of the routing provides the ORCA Foundry development tools with the necessary resources to route a design completely and to optimize the routing for system speed while reducing the overall power required by the device. Within each group of ten routing segments there is an equivalency of connectivity between pairs of segments. These pairs are segments: [0, 4] and [1, 5] and [2, 6] and [3, 7] and [8, 9]. The equivalency in connectivity ensures that signals on either segment in a pair have the same capability to get to a given destination. This, in turn, allows for signal distribution from a source to varying destinations without using special routing. It also provides for routing flexibility by ensuring that one segment position will not become so congested as to preclude routing a bus or group of signals and allows easy connectivity from either of the twin quads in a source PFU to either of the twin quads in any destination PFU. Having ten segments in a group is significant in that it provides for routing a byte of data and two control signals or parity. Due to the equivalent pairs of segments, this can also be viewed as routing two nibbles each with a control signal. Figure 19 is an overview of the routing for a single PLC. 5-5766(F) Figure 19. Single PLC View of Inter-PLC Route Segments 2 OF 5 LINE-BY-LINE FINS PFU OUTPUT SLIC SWITCHING SUR[9:0] hxH[9:0] hx1U[9:0] hCK FC SLL[9:0] hx1B[9:0] hx5[9:0] hxL[9:0] BR[9:0] SUL[9:0] BL[9:0] FC SUL[9:0] BR[9:0] LCK SLL[9:0] FC SLR[9:0] 5 2 5 2 5 2 KEY: CONFIGURABLE SIGNAL LINE BREAKS |
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