OR3TP12 datasheet(26/128 Pages) AGERE

Part #	OR3TP12

Description	Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

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ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

26

Lucent Technologies Inc.

Symbol

I/O

Description

Clock

Domain

Target Write Data FIFO Signals (continued)

twlastcycn

I

Target Write Last Data Cycle. This active-low signal has two functions:

a. Indicates that the current Target start address data on twdata (quad-port)

or datatofpga (dual-port with fifo_sel = 1) is the final transfer of the

address phase. taenn is required to be asserted to receive twlastcycn.

b. Indicates that the current Target write data on twdata (quad-port) or

datatofpga (dual-port with fifo_sel = 1) is the final transfer of the data

phase. For single data transfers, it will be asserted on the only word of the

transfer, whereas on bursts, if will be asserted only on the final word.

twdataenn is required to be asserted to receive twlastcycn.

fclk*

twburstpendn

O

Burst Write Data Control. This active-low signal indicates to the Target con-

troller that a write transaction should not be disconnected immediately when

the Target write data FIFO is full, but allow up to eight wait-states to be

inserted. When desasserted, the Target controller will disconnect when the

write FIFOs are full. Once asserted, this signal needs to remain asserted for

a minimum of two pciclk cycles.

pciclk

Target Read Data FIFO Signals

trdataenn

O

Target Read FIFO Data Enable. This active-low signal enables the register-

ing of bus trdata (quad-port mode) or datafmfpga (dual-port mode) into the

Target read data FIFO. trdataenn should not be asserted when the Target

read data FIFO is full (tr_fulln = 0).

fclk*

trdata[17:0]

(quad-port mode)

or

datafmfpga[31:0],

datafmfpgax[3:0]

(dual-port mode)

O

Depending on the OR3TP12 configuration, only one of these buses will be

available to the FPGA application. For Target operations, these buses will

carry the same information, but in different sizes as summarized below:

Target Read Data: Read data to the PCI bus.

Data:

trdata[15:0]

datafmfpga[31:0]

Unused:

trdata[17:16]

datafmfpgax[3:0]

fclk*

tr_afulln

I

Target Read FIFO Almost Full. This active-low signal indicates that the Tar-

get read data FIFO has only four more 64-bit empty locations available.

fclk*

tr_fulln

I

Target Read FIFO Full. This active-low signal indicates that the Target read

data FIFO is full and that no more data can be accepted. trdataenn must not

be asserted when tr_fulln is asserted.

fclk*

trlastcycn

I

Target Read Last Data Cycle. This active-low signal is asserted to indicate

the final cycle of the read data phase. During read bursts, more than one

clock is usually required to transfer a complete data phase; therefore, this

signal will be asserted only on the last data word. During a read burst, trlast-

cycn may remain inactive for longer than it is required by the external

Master, leading to transfer of excess data into the Target read data FIFO. All

excess data will be cleared when the external Master terminates the transac-

tion. trlastcycn will only be active only with an asserted trdataenn.

fclk*

* The source of the clock (fclk1 or fclk2) for the FIFO interface (Master or Target) is selected in the FPSC configuration manager.

PCI Bus Core Detailed Description (continued)

Table 6. Embedded Core/FPGA Interface Signals (continued)

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