Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

OR3T20 Datasheet(PDF) 84 Page - Agere Systems

Part # OR3T20
Description  3C and 3T Field-Programmable Gate Arrays
Download  210 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AGERE [Agere Systems]
Direct Link  
Logo AGERE - Agere Systems

OR3T20 Datasheet(HTML) 84 Page - Agere Systems

Back Button OR3T20 Datasheet HTML 80Page - Agere Systems OR3T20 Datasheet HTML 81Page - Agere Systems OR3T20 Datasheet HTML 82Page - Agere Systems OR3T20 Datasheet HTML 83Page - Agere Systems OR3T20 Datasheet HTML 84Page - Agere Systems OR3T20 Datasheet HTML 85Page - Agere Systems OR3T20 Datasheet HTML 86Page - Agere Systems OR3T20 Datasheet HTML 87Page - Agere Systems OR3T20 Datasheet HTML 88Page - Agere Systems Next Button
Zoom Inzoom in Zoom Outzoom out
 84 / 210 page
background image
84
84
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
High-Speed Internal Processing with Slow I/Os
The PCM PLL mode provides two outputs, one sent to
the global system clock routing of the FPGA and the
other to the ExpressCLK(s) that serve the FPGA I/Os.
The ExpressCLK output of the PCM has a divide capa-
bility (DIV2) that the system clock output does not. This
feature allows an input clock to be multiplied up to a
higher frequency for high-speed internal processing,
and also allows the ExpressCLK output to be divided
down to a lower frequency to accommodate off-FPGA
data transfers. For example, a 10 MHz input clock may
be multiplied (see Clock Multiplication in the Phase-
Locked Loop (PLL) Mode subsection) to 25 MHz (DIV0
= 4, DIV1 = 5, DIV2 = 2) and output to the FPGA
ExpressCLK
. This allows the I/Os of the circuit to run at
25 MHz ((2 * 5)/4 * 10 MHz). The system clock will run
at DIV2 times the ExpressCLK rate, which is 2 times
25 MHz, or 50 MHz. This setup allows for internal pro-
cessing to occur at twice the rate of on/off device I/O
transfers.
PCM Cautions
Cautions do apply when using the PCM. There are a
number of configurations that are possible in the PCM
that are theoretically valid, but may not produce viable
results. This section describes some of those situa-
tions, and should leave the user with an understanding
of the types of pitfalls that must be avoided when modi-
fying clock signals.
Resultant signals from the PCM must meet the FPGA
timing specifications. It is possible to specify pulses by
using duty-cycle adjustments that are too narrow to
function in the FPGA. For instance, if a 40 MHz clock is
doubled to 80 MHz and a 6.25% duty cycle is selected,
the result will be a 780 ps pulse that repeats every
12.5 ns. This pulse falls outside of the clock pulse width
specification and is not valid.
Using divider DIV2, it is possible to specify a clock mul-
tiplication factor of 64 between the input clock and the
output system clock. As mentioned above, the resultant
frequency must meet all FPGA timing specifications.
The input clock must also meet the minimum specifica-
tions. An input clock rate that is below the PCM clock
minimum cannot be used even if the multiplied output is
within the allowable range.
The use of the PCM to tweak a clock signal to eliminate
a particular problem, such as a single setup time viola-
tion, is discouraged. A small shift in delay, duty cycle, or
phase to correct a single-point problem is in essence
an asynchronous patch to a synchronous system, mak-
ing the system less stable. This type of local problem,
as opposed to a global clock control issue like device-
wide clock delay, can usually be eliminated through
more robust design practices. If this type of change is
made, the designer must be aware that depending on
the extent of the change made, the design may fail to
operate correctly in a different speed grade or voltage
grade (e.g., 3C vs. 3T), or even in a different production
lot of the same device.
Divider DIV2 is available in DLL mode for the Express-
CLK
output, but its use is not recommended with duty-
cycle adjusted clocks.


Similar Part No. - OR3T20

ManufacturerPart #DatasheetDescription
logo
Agere Systems
OR3T20 AGERE-OR3T20 Datasheet
4Mb / 210P
   3C and 3T Field-Programmable Gate Arrays
OR3T20-5BA256 AGERE-OR3T20-5BA256 Datasheet
4Mb / 210P
   3C and 3T Field-Programmable Gate Arrays
OR3T20-5BA256I AGERE-OR3T20-5BA256I Datasheet
4Mb / 210P
   3C and 3T Field-Programmable Gate Arrays
OR3T20-5BA352 AGERE-OR3T20-5BA352 Datasheet
4Mb / 210P
   3C and 3T Field-Programmable Gate Arrays
OR3T20-5BA352I AGERE-OR3T20-5BA352I Datasheet
4Mb / 210P
   3C and 3T Field-Programmable Gate Arrays
More results

Similar Description - OR3T20

ManufacturerPart #DatasheetDescription
logo
Agere Systems
OR3C80-4PS240 AGERE-OR3C80-4PS240 Datasheet
4Mb / 210P
   3C and 3T Field-Programmable Gate Arrays
logo
List of Unclassifed Man...
OR2C04A ETC-OR2C04A Datasheet
3Mb / 192P
   Field-Programmable Gate Arrays
logo
Xilinx, Inc
DS022-1 XILINX-DS022-1 Datasheet
89Kb / 5P
   Field Programmable Gate Arrays
DS022 XILINX-DS022 Datasheet
1Mb / 233P
   Field Programmable Gate Arrays
logo
Agere Systems
OR4E2 AGERE-OR4E2 Datasheet
3Mb / 124P
   Field-Programmable Gate Arrays
logo
Lattice Semiconductor
OR2C04A LATTICE-OR2C04A Datasheet
3Mb / 192P
   Field-Programmable Gate Arrays
logo
List of Unclassifed Man...
ATT3000 ETC1-ATT3000 Datasheet
498Kb / 80P
   Field-Programmable Gate Arrays
logo
Texas Instruments
TPC10 TI-TPC10 Datasheet
3Mb / 69P
[Old version datasheet]   CMOS FIELD-PROGRAMMABLE GATE ARRAYS
logo
ATMEL Corporation
AT6000 ATMEL-AT6000 Datasheet
591Kb / 28P
   Coprocessor Field Programmable Gate Arrays
logo
Xilinx, Inc
XC4000E XILINX-XC4000E Datasheet
712Kb / 68P
   XC4000E and XC4000X Series Field Programmable Gate Arrays
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com