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OR3T20 Datasheet(PDF) 84 Page - Agere Systems |
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OR3T20 Datasheet(HTML) 84 Page - Agere Systems |
84 / 210 page 84 84 Lucent Technologies Inc. Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) High-Speed Internal Processing with Slow I/Os The PCM PLL mode provides two outputs, one sent to the global system clock routing of the FPGA and the other to the ExpressCLK(s) that serve the FPGA I/Os. The ExpressCLK output of the PCM has a divide capa- bility (DIV2) that the system clock output does not. This feature allows an input clock to be multiplied up to a higher frequency for high-speed internal processing, and also allows the ExpressCLK output to be divided down to a lower frequency to accommodate off-FPGA data transfers. For example, a 10 MHz input clock may be multiplied (see Clock Multiplication in the Phase- Locked Loop (PLL) Mode subsection) to 25 MHz (DIV0 = 4, DIV1 = 5, DIV2 = 2) and output to the FPGA ExpressCLK . This allows the I/Os of the circuit to run at 25 MHz ((2 * 5)/4 * 10 MHz). The system clock will run at DIV2 times the ExpressCLK rate, which is 2 times 25 MHz, or 50 MHz. This setup allows for internal pro- cessing to occur at twice the rate of on/off device I/O transfers. PCM Cautions Cautions do apply when using the PCM. There are a number of configurations that are possible in the PCM that are theoretically valid, but may not produce viable results. This section describes some of those situa- tions, and should leave the user with an understanding of the types of pitfalls that must be avoided when modi- fying clock signals. Resultant signals from the PCM must meet the FPGA timing specifications. It is possible to specify pulses by using duty-cycle adjustments that are too narrow to function in the FPGA. For instance, if a 40 MHz clock is doubled to 80 MHz and a 6.25% duty cycle is selected, the result will be a 780 ps pulse that repeats every 12.5 ns. This pulse falls outside of the clock pulse width specification and is not valid. Using divider DIV2, it is possible to specify a clock mul- tiplication factor of 64 between the input clock and the output system clock. As mentioned above, the resultant frequency must meet all FPGA timing specifications. The input clock must also meet the minimum specifica- tions. An input clock rate that is below the PCM clock minimum cannot be used even if the multiplied output is within the allowable range. The use of the PCM to tweak a clock signal to eliminate a particular problem, such as a single setup time viola- tion, is discouraged. A small shift in delay, duty cycle, or phase to correct a single-point problem is in essence an asynchronous patch to a synchronous system, mak- ing the system less stable. This type of local problem, as opposed to a global clock control issue like device- wide clock delay, can usually be eliminated through more robust design practices. If this type of change is made, the designer must be aware that depending on the extent of the change made, the design may fail to operate correctly in a different speed grade or voltage grade (e.g., 3C vs. 3T), or even in a different production lot of the same device. Divider DIV2 is available in DLL mode for the Express- CLK output, but its use is not recommended with duty- cycle adjusted clocks. |
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