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LU5X34F Datasheet(PDF) 4 Page - Agere Systems |
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LU5X34F Datasheet(HTML) 4 Page - Agere Systems |
4 / 26 page 4 4 Lucent Technologies Inc. LU5X34F Preliminary Data Sheet Quad Gigabit Ethernet Transceiver July 2000 Functional Description (continued) Byte Alignment When ENCDET = 1, the LU5X34F recognizes the comma character and aligns this 10-bit character to the word boundary, bits RX[0:9]. COMDET =1 when the parallel output word contains a byte-aligned comma character. The COMDET flag will continue to pulse a logic 1 whenever a byte-aligned comma character is at the parallel output port, indepen- dent of ENCDET. When ENCDET = 0, there are two possible scenarios depending upon when the comma character is received. 1. If byte alignment had been previously achieved when ENCDET had been a logic 1, the COMDET flag will continue to pulse a logic 1 whenever a byte-aligned comma character is at the parallel output port. If a comma character occurs that is not on the word boundary, no attempt will be made to align this comma character and the COMDET flag will remain at a logic 0. 2. If byte alignment had not been previously achieved when ENCDET had been a logic 1, then the first (and only the first) comma character received will be aligned to the word boundary. COMDET will pulse when the comma character is aligned to the word boundary. Parallel Output Port Timing for the parallel output data and the 50 MHz to 62.5 MHz receive-byte clock is given in Table 14. Two low data rate receive-byte clocks are available as TTL compatible outputs during use of the parallel out- put port in 10-bit mode. RXCLK1 is the receive byte clock used by the protocol device to register bytes 0 and 2. RXCLK0 is the receive-byte clock used by the protocol device to register bytes 1 and 3, and it is 180 degrees out of phase with RXCLK1. Both RXCLK1 and RXCLK0 can be stretched during byte alignment but not truncated or slivered. The maximum allowable frequency of these two clocks under all circumstances, excluding start-up, will not exceed 80 MHz. The start- up time is specified as 1 ms. Loopback Mode Operation A control signal input, EWRAP, selects between two possible sets of inputs: normal data (HDINP, HDINN) or internal loopback data. When EWRAP = 1, the serial output ports, HDOUTP and HDOUTN, remain active. The serial transmit data prior to the PECL output driver is directed to the data recovery circuit, where clock is recovered and data is resynchronized to the recovered clock. Retimed data and clock then go to the serial-to- parallel converter. Table 2. Definition of Bit Transmission/Reception Order* * Lower case X signifies channel A, B, C, or D. Serial Transmit/ Receive Rate TXX[9:0] RXX[9:0] 1.0 Gbits/s to 1.25 Gbits/s TXX[0] bit serially transmitted first at HDOUTXP, HDOUTXN RXX[0] bit received first at serial inputs HDINXP, HDINXN |
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