 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LU3X34FTR-HS128-DB Datasheet(PDF) 8 Page - Agere Systems |
|
||||||||||||||||||||||||||||||
LU3X34FTR-HS128-DB Datasheet(HTML) 8 Page - Agere Systems |
|
|
8 / 52 page  LU3X34FTR Preliminary Data Sheet Quad 3 V 10/100 Ethernet Transceiver TX/FX July 2000 8 Lucent Technologies Inc. Pin Descriptions (continued) Table 2. Twisted-Pair Magnetic Interface Table 3. Twisted-Pair Transceiver Control/Transmitter Control Table 4. MII Interface (RMII Mode) Pin No. Pin Name I/O Pin Description 6, 11, 28, 33 7, 10, 29, 32 TX+_[0:3] TX–_[0:3] O Transmit Driver Pairs. These pins are used to transmit 100Base-T MLT-3 signals across Category 5 UTP cable. 10Base-T Manchester signals across Category 3, 4, or 5 UTP cable in twisted-pair opera- tion or PECL data in fiber mode. 3, 14, 25, 36 2, 15, 24, 37 RX–_[0:3] RX+_[0:3] I Receive Pair. These pins receive 100Base-T MLT-3 data or 10Base-T Manchester data from the UTP cable in twisted-pair mode or PECL data in fiber mode. Pin No. Pin Name I/O Pin Description 5, 12, 27, 34 REF100_[0:3] I Reference Pin for 100 Mbits/s Twisted-Pair Driver. The value of the connected resistor is 301 Ω. 22 REF10 I Reference Pin for 10 Mbits/s Twisted-Pair Driver. The value for the connected resistor is 4.65 k Ω. 127 ER I Transmit Driver Edge Rate Control. When set to 1, the rise time of the transmit data will be less than 3.5 ns. 41 TPTXTR I Network Interface 3-State Control. When high, the transmit drivers for the four ports are 3-stated. Pin No. Pin Name* I/O Pin Description 99, 73, 53 TXEN_[1:3] I Transmit Enable for Ports 1—3. 113 TXEN_0 I Transmit Enable for Port 0. 102 RMII_RXER_0 I/O Receiver Error Output for Port 0. Indicates an illegal code-group has been received. 112, 111 RMII_TXD_0[0:1] I Transmit Data for Port 0. 110, 109 RMII_RXD_0[0:1] I/O Receive Data for Port 0. 101 CRS_DV_0/SMII_EN I/O ↓ CRS_DV Output for Port 0. During reset, this is an input pin; logic level of 0 at this pin enables RMII mode. This pin has an internal 40 k Ω pull-down resistor that sets the MII interface to RMII mode with- out an external component. After reset, CRS_DV output for port 0 is asserted only during receive activity. 98, 97 RMII_TXD_1[0:1] I/O Transmit Data for Port 1. 96, 95 RMII_RXD_1[0:1] O Receive Data for Port 1. 94 CRS_DV_1/PHYAD[2] I/O ↓ CRS_DV Output for Port 1. During reset, this is an input pin for PHY_address[2] configuration. This pin has an internal 40 k Ω pull-down resistor that sets the PHY_AD[2] to a 0 without an external component. After reset, CRS_DV output for port 1 and is asserted only during receive activity. |
Similar Part No. - LU3X34FTR-HS128-DB |
|
Similar Description - LU3X34FTR-HS128-DB |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
