Electronic Components Datasheet Search |
|
LU3X31T-T64 Datasheet(PDF) 6 Page - Agere Systems |
|
LU3X31T-T64 Datasheet(HTML) 6 Page - Agere Systems |
6 / 44 page LU3X31T-T64 Single-Port 3 V Preliminary Data Sheet 10/100 Ethernet Transceiver TX July 2000 6 Lucent Technologies Inc. Pin Descriptions Table 2. Twisted-Pair Transceiver Control Table 3. MII Interface Note: Smaller font indicates that the pin has multiple functions. Pin No. Pin Name I/O Pin Description 50 REF100 I Reference Resistor for 100 Mbits/s Twisted-Pair Driver. Connect this pin to ground through a 301 Ω resistor. 49 REF10 I Reference Resistor for 10 Mbits/s Twisted-Pair Driver. Connect this pin to ground through a 4.64 k Ω resistor. 5TPTXTR I Twisted-Pair Transmitter 3-State. A high on this pin will 3-state the twisted-pair outputs. Tie to ground in normal operation. Pin No. Pin Name I/O Pin Description 18 RXDV O Receive Data Valid. Signals the presence of data on RXD[3:0]. 19 RXER O Receive Error. Indicates a received coding error has occurred. 20 RXD3 O Receive Data[3]. 21 RXD2 O Receive Data[2]. 22 RXD1 O Receive Data[1]. 23 RXD0 O Receive Data[0]. 24 RXCLK O Receive Clock. 27 TXEN I Transmit Enable. Signals the presence of data on TXD[3:0]. 28 TXER I Transmit Error. Indicates a transmit coding error has occurred. 29 TXD3 I Transmit Data[3]. 30 TXD2 I Transmit Data[2]. 31 TXD1 I Transmit Data[1]. 32 TXD0 I Transmit Data[0]. 33 TXCLK O Transmit Clock. 34 CRS/PHY[3] I/O Carrier Sense/PHY Address[3]. This output pin indicates the carrier sense condition. See Table 4 for PHY[3] description. 39 COL/PHY[4] I/O Collision/False Carrier Sense. This output pin indicates collision condition in normal MII operation and is squelch jabber in 10 Mbits/s mode. See Table 4 for PHY[4] description. 35 MDIO I/O Management Data I/O. Serial access to device config registers. 45 MDC I Management Data Clock. Clock for R/W of device config registers. 16 MDIOINTZ/PHY[2] I/O MDIO Interrupt (Active-Low). The MDIO interrupt pin outputs a logic 0 pulse of 40 ns, synchronous to XIN, whenever an unmasked inter- rupt condition is detected. Refer to management registers 1Dh and 1Eh for interrupt conditions. See Table 4 for PHY[2] description. |
Similar Part No. - LU3X31T-T64 |
|
Similar Description - LU3X31T-T64 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |