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DSP16410C Datasheet(PDF) 67 Page - Agere Systems |
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DSP16410C Datasheet(HTML) 67 Page - Agere Systems |
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67 / 373 page  List of Tables (continued) Table Page Agere Systems Inc. Agere Systems—Proprietary 11 Use pursuant to Company instructions Data Sheet June 2001 DSP16410B Digital Signal Processor ®Table 103. SCON2 (SIU Output Frame Control) Register................................................................................ 184 ®Table 104. SCON3 (SIU Input/Output Subframe Control) Register ................................................................. 185 ®Table 105. SCON4 (SIU Input Even Subframe Valid Vector Control) Register................................................ 186 ®Table 106. SCON5 (SIU Input Odd Subframe Valid Vector Control) Register ................................................. 186 ®Table 107. SCON6 (SIU Output Even Subframe Valid Vector Control) Register............................................. 187 ®Table 108. SCON7 (SIU Output Odd Subframe Valid Vector Control) Register .............................................. 187 ®Table 109. SCON8 (SIU Output Even Subframe Mask Vector Control) Register ............................................ 187 ®Table 110. SCON9 (SIU Output Odd Subframe Mask Vector Control) Register.............................................. 187 ®Table 111. SCON10 (SIU Input/Output General Control) Register .................................................................. 188 ®Table 112. SCON11 (SIU Input/Output Active Clock Control) Register ........................................................... 191 ®Table 113. SCON12 (SIU Input/Output Active Frame Sync Control) Register................................................. 192 ®Table 114. SIDR (SIU Input Data) Register...................................................................................................... 193 ®Table 115. SODR (SIU Output Data) Register ................................................................................................. 193 ®Table 116. STAT (SIU Input/Output General Status) Register ......................................................................... 194 ®Table 117. FSTAT (SIU Input/Output Frame Status) Register.......................................................................... 194 ®Table 118. OCIX 〈〈〈〈0—1〉〉〉〉 and ICIX〈〈〈〈0—1〉〉〉〉 (SIU Output and Input Channel Index) Registers ............................. 195 ®Table 119. OCIX 〈〈〈〈0—1〉〉〉〉 (SIU Output Channel Index) Registers....................................................................... 195 ®Table 120. ICIX 〈〈〈〈0—1〉〉〉〉 (SIU Input Channel Index) Registers ........................................................................... 196 ®Table 121. Source Clock Selection .................................................................................................................. 197 ®Table 122. pllcon (Phase-Lock Loop Control) Register................................................................................... 199 ®Table 123. pllfrq (Phase-Lock Loop Frequency Control) Register .................................................................. 199 ®Table 124. plldly (Phase-Lock Loop Delay Control) Register.......................................................................... 199 ®Table 125. Wake-Up Latency and Power Consumption for Low-Power Standby Mode .................................. 202 ®Table 126. Core Boot-Up After Reset............................................................................................................... 205 ®Table 127. Contents of IROM0 and IROM1 Boot ROMs.................................................................................. 205 ®Table 128. DSP16410B Instruction Groups ..................................................................................................... 207 ®Table 129. Instruction Set Summary ................................................................................................................ 209 ®Table 130. Notation Conventions for Instruction Set Descriptions ................................................................... 215 ®Table 131. Overall Replacement Table ............................................................................................................ 216 ®Table 132. F1 Instruction Syntax...................................................................................................................... 219 ®Table 133. F1E Function Statement Syntax..................................................................................................... 221 ®Table 134. DSP16410B Conditional Mnemonics ............................................................................................. 223 ®Table 135. Program-Accessible (Register-Mapped) Registers by Type, Listed Alphabetically........................ 226 ®Table 136. DMAU Memory-Mapped Registers................................................................................................. 229 ®Table 137. SEMI Memory-Mapped Registers .................................................................................................. 230 ®Table 138. PIU Registers ................................................................................................................................. 231 ®Table 139. SIU Memory-Mapped Registers ..................................................................................................... 231 ®Table 140. alf (AWAIT Low-Power and Flag) Register .................................................................................... 232 ®Table 141. auc0 (Arithmetic Unit Control 0) Register....................................................................................... 233 ®Table 142. auc1 (Arithmetic Unit Control 1) Register....................................................................................... 234 ®Table 143. cbit (BIO Control) Register............................................................................................................. 235 ®Table 144. cloop (Cache Loop) Register ......................................................................................................... 236 ®Table 145. csave (Cache Save) Register ........................................................................................................ 236 ®Table 146. cstate (Cache State) Register........................................................................................................ 236 ®Table 147. imux (Interrupt Multiplex Control) Register .................................................................................... 237 ®Table 148. ID (JTAG Identification) Register.................................................................................................... 238 ®Table 149. inc0 and inc1 (Interrupt Control) Registers 0 and 1....................................................................... 238 ®Table 150. ins (Interrupt Status) Register ........................................................................................................ 239 ®Table 151. mgi (Core-to-Core Message Input) Register.................................................................................. 239 ®Table 152. mgo (Core-to-Core Message Output) Register.............................................................................. 239 ®Table 153. pid (Processor Identification) Register ........................................................................................... 239 |
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