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DSP16410C Datasheet(PDF) 12 Page - Agere Systems |
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DSP16410C Datasheet(HTML) 12 Page - Agere Systems |
12 / 373 page Data Addendum May 2001 DSP16410C Digital Signal Processor Agere Systems Inc. 12 5 Ball Grid Array Information (continued) 5.2 256-Ball EBGA Package (continued) Table 3. 256-Ball EBGA Ball Assignments Sorted Alphabetically by Symbol (continued) Symbol PBGA Coordinate Type Description POBE V10 O PIU Output Buffer Empty Flag. PODS V8 I PIU Output Data Strobe. PRDY V9 O PIU Host Ready. PRDYMD W8 I PRDY Mode. PRWN W7 I PIU Read/Write (negative assertion). RSTN K17 I Device Reset (negative assertion). SCK0 P20 I External Clock for SIU0 Active Generator. SCK1 T2 I External Clock for SIU1 Active Generator. SICK0 M17 I/O SIU0 Input Clock. SICK1 V1 I/O SIU1 Input Clock. SID0 P19 I SIU0 Input Data. SID1 R3 I SIU1 Input Data. SIFS0 M19 I/O SIU0 Input Frame Sync. SIFS1 U2 I/O SIU1 Input Frame Sync. SOCK0 N18 I/O SIU0 Output Clock. SOCK1 R4 I/O SIU1 Output Clock. SOD0 P18 O/Z SIU0 Output Data. SOD1 P4 O/Z SIU1 Output Data. SOFS0 N17 I/O SIU0 Output Frame Sync. SOFS1 U1 I/O SIU1 Output Frame Sync. TCK0 H19 I JTAG Test Clock for CORE0. TCK1 N2 I JTAG Test Clock for CORE1. TDI0 J17 I JTAG Test Data Input for CORE0. TDI1 M2 I JTAG Test Data Input for CORE1. TDO0 F19 O JTAG Test Data Output for CORE0. TDO1 R2 O JTAG Test Data Output for CORE1. TMS0 H20 I JTAG Test Mode Select for CORE0. TMS1 N1 I JTAG Test Mode Select for CORE1. TRAP K20 I/O TRAP/Breakpoint Indication. TRST0N H18 I JTAG TAP Controller Reset for CORE0 (negative assertion). TRST1N N3 I JTAG TAP Controller Reset for CORE1 (negative assertion). VDD1 B18, C5, C7, C9, C10, D3, D9, D12, D13, E18, G1, G18, J2, K19, L3, M3, M4, N19, P3, T3, T17, U8, U9, U12, V11, V12, V14, V16, W3 P Power Supply for Internal Circuitry. VDD1A J18 P Power Supply for PLL Circuitry. VDD2 A2, A7, A11, A15, A19, B1, B20, D8, D11, D14, F1, G4, G20, H17, K1, K4, L17, L20, N4, P1, P17, R20, U7, U10, U13, W1, W20, Y2, Y6, Y10, Y14, Y19 P Power Supply for External Circuitry (I/O). |
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