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DSP1629 Datasheet(PDF) 25 Page - Agere Systems |
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DSP1629 Datasheet(HTML) 25 Page - Agere Systems |
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25 / 114 page  Preliminary Data Sheet February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 23 4 Hardware Architecture (continued) While ILD1 and OLD1 are not required externally for multiprocessor operation, they are used internally in the DSP's SIO. Setting the LD field of the master's sioc reg- ister to a logic level 1 will ensure that the active genera- tion of SYNC1, ILD1, and OLD1 is derived from OCK1 (see Table 26). With this configuration, all DSPs should use ICK1 (tied to OCK1) in passive mode to avoid con- flicts on the clock (CK) line (see the DSP1611/17/18/27 Digital Signal Processor Information Manual for more information). Four registers (per SIO) configure the multiprocessor mode: the time-division multiplexed slot register (tdms or tdms2), the serial receive and transmit address reg- ister (srta or srta2), the serial data transmit register (sdx or sdx2), and the multiprocessor serial address/ protocol register (saddx or saddx2). Multiprocessor mode requires no external logic and uses a TDM interface with eight 16-bit time slots per frame. The transmission in any time slot consists of 16 bits of serial data in the data channel and 16 bits of address and protocol information in the address/proto- col channel. The address information consists of the transmit address field of the srta register of the trans- mitting device. The address information is transmitted concurrently with the transmission of the first 8 bits of data. The protocol information consists of the transmit protocol field written to the saddx register and is trans- mitted concurrently with the last 8 bits of data (see Table 29, Multiprocessor Protocol Register). Data is re- ceived or recognized by other DSP(s) whose receive address matches the address in the address/protocol channel. Each SIO port has a user-programmable re- ceive address and transmit address associated with it. The transmit and receive addresses are programmed in the srta register. In multiprocessor mode, each device can send data in a unique time slot designated by the tdms register transmit slot field (bits 7—0). The tdms register has a fully decoded transmit slot field in order to allow one DSP1628 device to transmit in more than one time slot. This procedure is useful for multiprocessor systems with less than eight DSP1628 devices when a higher bandwidth is necessary between certain devices in that system. The DSP operating during time slot 0 also drives SYNC1. In order to prevent multiple bus drivers, only one DSP can be programmed to transmit in a particular time slot. In addition, it is important to note that the address/pro- tocol channel is 3-stated in any time slot that is not being driven. Therefore, to prevent spurious inputs, the address/pro- tocol channel should be pulled up to VDD with a 5 k Ω re- sistor, or it should be guaranteed that the bus is driven in every time slot. (If the SYNC1 signal is externally gen- erated, then this pull-up is required for correct initializa- tion.) Each SIO also has a fully decoded transmitting address specified by the srta register transmit address field (bits 7—0). This is used to transmit information regarding the destination(s) of the data. The fully decoded receive ad- dress specified by the srta register receive address field (bits 15—8) determines which data will be received. The SIO protocol channel data is controlled via the saddx register. When the saddx register is written, the lower 8 bits contain the 8-bit protocol field. On a read, the high- order 8 bits read from saddx are the most recently re- ceived protocol field sent from the transmitting DSP's saddx output register. The low-order 8 bits are read as 0s. An example use of the protocol channel is to use the top 3 bits of the saddx value as an encoded source address for the DSPs on the multiprocessor bus. This leaves the remaining 5 bits available to convey additional control information, such as whether the associated field is an opcode or data, or whether it is the last word in a trans- fer, etc. These bits can also be used to transfer parity in- formation about the data. Alternatively, the entire field can be used for data transmission, boosting the band- width of the port by 50%. Using SIO2 The SIO2 functions the same as the SIO. Please refer to Pin Multiplexing in Section 4.1 for a description of pin multiplexing of BIO, PHIF, VEC[3:0], and SIO2. |
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