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DSP1629 Datasheet(PDF) 90 Page - Agere Systems |
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DSP1629 Datasheet(HTML) 90 Page - Agere Systems |
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90 / 114 page  Preliminary Data Sheet February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 88 10 Timing Characteristics for 2.7 V Operation (continued) 10.2 Reset Circuit The DSP1628 has two external reset pins: RSTB and TRST. At initial powerup, or if the supply voltage falls below VDD MIN* and a device reset is required, both TRST and RSTB must be asserted to initialize the device. Figure 12 shows two separate events: 1. Chip reset at initial powerup. 2. Chip reset following a drop in power supply. Note: The TRST pin must be asserted even if the JTAG controller is not used by the application. * See Table 60, Recommended Operating Conditions. * When both INT0 and RSTB are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a 3-state condition. With RSTB asserted and INT0 not asserted, EROM, ERAMHI, ERAMLO, IO, and RWN outputs remain high, and CKO remains a free-running clock. † See Table 62 for input clock electrical requirements. Figure 12. Powerup Reset and Chip Reset Timing Diagram Note: The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise, high currents may flow. Table 68. Timing Requirements for Powerup Reset and Chip Reset Abbreviated Reference Parameter Min Max Unit t8 RSTB and TRST Reset Pulse (low to high) 6T — ns t9 VDD Ramp — 10 ms t146 VDD MIN to RSTB Low CMOS Small-signal 2T 20 — — ns µs t153 RSTB (low to high) — 54 ns Table 69. Timing Characteristics for Powerup Reset and Chip Reset Abbreviated Reference Parameter Min Max Unit t10 RSTB Disable Time (low to 3-state) — 100 ns t11 RSTB Enable Time (high to valid) — 100 ns VDD RAMP RSTB, TRST OUTPUT PINS * CKI† t11 VOH VOL VIH VIL t9 t146 t10 0.4 V VDD MIN t11 VDD MIN 0.4 V t10 t9 t146 t153 t8 t153 t8 5-4010 (C).a |
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