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DSP16210 Datasheet(PDF) 71 Page - Agere Systems |
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DSP16210 Datasheet(HTML) 71 Page - Agere Systems |
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71 / 173 page  Data Sheet July 2000 DSP16210 Digital Signal Processor Lucent Technologies Inc. DRAFT COPY 71 Software Architecture (continued) Instruction Set Quick Reference (continued) Table 32. Instruction Set Summary Instruction Flags Cycles Words szlme Out In Multiply/Accumulate (MAC) Group F1 Yszlm– 1 1 1 F1 x 〈h,l〉=Y szlm– F1 y 〈h,l〉=Y szlm– F1 a 〈h,l〉=Y szlm– F1 Y=y 〈h,l〉 szlm– F1 Y=aT 〈h,l〉 szlm– F1 yh=aTh xh=X szlm– 1+XC† F1 yh=Y xh=X szlm– if CON F1E szlme 1 1 2 F1E yh,l=aTEh,l szlme F1E aTEh,l= yh,l szlme F1E y=aE_Ph szlme F1E aE_Ph=y szlme F1E x h,l =YE szlme F1E y h,l =YE szlme F1E aTE h,l =YE szlme F1E aE_Ph=YE szlme F1E YE=x h,l szlme F1E YE=y h,l szlme F1E YE=aTE h,l szlme F1E YE=aE_Ph szlme F1E yh=*r0 r0=rNE+jhb szlme F1E YE szlme F1E x h,l=XE szlme 1+XC† F1E aTE h,l =XE szlme F1E aE_Ph=XE szlme F1E y=aE_Ph x h=XE szlme F1E yh =aTEh x h=XE szlme F1E aTEh =yh x h=XE szlme F1E y h=YE‡ a4 h =XE szlme F1E y h,l =YE x h =XE szlme F1E YE=y h,l x h=XE szlme F1E y h =YE‡ a4_5h=XE szlme F1E YE=a6_7h x h =XE szlme F1E YE=a6 h‡ x h=XE szlme F1E YE=a6 h‡ a4 h=XE szlme †XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc- tion types and can only be avoided by use of the cache. ‡ For this transfer, the postincrement options *rME and *rME– – are not available for double-word loads. § The – (40-bit subtraction) operation is encoded as aDE = aSE + IM16 with the IM16 value negated. †† For conditional branch instructions, the execution time is two cycles if the branch is not taken. ‡‡ The instruction performs the same function whether or not near (optional) is included. §§ Not including the N instructions. D |
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