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DSP1620 Datasheet(PDF) 10 Page - Agere Systems |
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DSP1620 Datasheet(HTML) 10 Page - Agere Systems |
10 / 114 page Preliminary Data Sheet DSP1628 Digital Signal Processor February 1997 8 Lucent Technologies Inc. 4 Hardware Architecture The DSP1628 device is a 16-bit, fixed-point program- mable digital signal processor (DSP). The DSP1628 consists of a DSP1600 core together with on-chip mem- ory and peripherals. Added architectural features give the DSP1628 high program efficiency for signal coding applications. 4.1 DSP1628 Architectural Overview Figure 4 shows a block diagram of the DSP1628. The following modules make up the DSP1628. DSP1600 Core The DSP1600 core is the heart of the DSP1628 chip. The core contains data and address arithmetic units, and control for on-chip memory and peripherals. The core provides support for external memory wait-states and on-chip dual-port RAM and features vectored inter- rupts and a trap mechanism. Dual-Port RAM (DPRAM) The DSP1628x16 contains 16 banks of zero wait-state memory and the DSP1628x08 contains 8 banks of zero wait-state memory. Each bank consists of 1K 16-bit words and has separate address and data ports to the instruction/coefficient and data memory spaces. A pro- gram can reference memory from either space. The DSP1600 core automatically performs the required mul- tiplexing. If references to both ports of a single bank are made simultaneously, the DSP1600 core automatically inserts a wait-state and performs the data port access first, followed by the instruction/coefficient port access. A program can be downloaded from slow, off-chip mem- ory into DPRAM, and then executed without wait-states. DPRAM is also useful for improving convolution perfor- mance in cases where the coefficients are adaptive. Since DPRAM can be downloaded through the JTAG port, full-speed remote in-circuit emulation is possible. DPRAM can also be used for downloading self-test code via the JTAG port. Read-Only Memory (ROM) The DSP1628 contains 48K 16-bit words of zero wait- state mask-programmable ROM for program and fixed coefficients. External Memory Multiplexer (EMUX) The EMUX is used to connect the DSP1628 to external memory and I/O devices. It supports read/write opera- tions from/to instruction/coefficient memory (X memory space) and data memory (Y memory space). The DSP1600 core automatically controls the EMUX. In- structions can transparently reference external memory from either set of internal buses. A sequencer allows a single instruction to access both the X and the Y exter- nal memory spaces. Clock Synthesis The DSP powers up with a 1X input clock (CKI/CKI2) as the source for the processor clock. An on-chip clock synthesizer (PLL) can also be used to generate the sys- tem clock for the DSP, which will run at a frequency mul- tiple of the input clock. The clock synthesizer is deselected and powered down on reset. For low-power operation, an internally generated slow clock can be used to drive the DSP. If both the clock synthesizer and the internally generated slow clock are selected, the slow clock will drive the DSP; however, the synthesizer will continue to run. The clock synthesizer and other programmable clock sources are discussed in Section 4.13. The use of these programmable clock sources for power management is discussed in Section 4.14. |
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