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DSP1620 Datasheet(PDF) 1 Page - Agere Systems |
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DSP1620 Datasheet(HTML) 1 Page - Agere Systems |
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1 / 114 page  Advisory May 1999 DRAFT COPY Clarification to the Serial I/O Control Register Description for the DSP1620/27/28/29 Devices Active Clock Frequency The purpose of this advisory is to clarify the function of the serial I/O control registers in the DSP1620/27/28/29 devices. Specifically, it clarifies the function of the control register field that specifies the active clock frequency. The device data sheets state that the active clock frequency is a ratio of the input clock frequency on the CKI pin (DSP1627/28/29 devices) or the output clock frequency on the CKO pin (DSP1620 device). For all four devices, the actual active clock frequency is a ratio of the internal clock frequency, which can be programmed as either the input clock frequency on the CKI pin or the output of an internal clock synthesizer (PLL). Table 1 summarizes information for each of the four devices. It lists the document number for each device data sheet. For example, the data sheet for the DSP1620, entitled DSP1620 Digital Signal Processor, has the docu- ment number DS97-321WDSP. Table 1 also lists the name of each serial I/O unit on each device, the corre- sponding control register, the data sheet page number that describes the register, and the corresponding field within the register that specifies the active clock frequency. For example, the DSP1620 contains two serial I/O units named SIO and SSIO. The control register for SIO is sioc described on page 94 of the data sheet. Bits 8—7 within sioc (CLK1 field) specify the active clock frequency of the SIO. Table 2 shows a corrected description of the CLK/CLK1/CLK2 field of the serial I/O control register. The specific correction is shown in bold type—the active clock frequency is a ratio of finternal clock, not of CKI or CKO. Table 1. Data Sheet and Serial I/O Information for the DSP1620/27/28/29 Devices Device Data Sheet Document Number Serial I/O Units Name Control Register Data Sheet Page No. Active Clock Frequency Control Field Bits Name DSP1620 DS97-321WDSP SIO sioc 94 8—7 CLK1 SSIO SSIOC 96 8—7 CLK2 DSP1627 DS96-188WDSP SIO sioc 45 8—7 CLK SIO2 DSP1628 DS97-040WDSP SIO sioc 55 8—7 CLK SIO2 DSP1629 DS96-039WDSP SIO sioc 46 8—7 CLK SIO2 Table 2. Corrected Description of CLK/CLK1/CLK2 Field Field Value Description CLK CLK1 CLK2 00 01 10 11 Active clock frequency = finternal clock ÷ 2 Active clock frequency = finternal clock ÷ 6 Active clock frequency = finternal clock ÷ 8 Active clock frequency = finternal clock ÷ 10 |
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