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DNC3X3125 Datasheet(PDF) 11 Page - Agere Systems |
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DNC3X3125 Datasheet(HTML) 11 Page - Agere Systems |
11 / 32 page Advance Data Sheet DNC3X3125 March 2000 10/100 Mbits/s Ethernet Transceiver Macrocell 11 4 SDFX PAD (optional I) SDFX. Signal detect from fiber-optic receiver. This pad does not have to be bonded out if fiber mode is not used. SECUR I Security. When this input is high and MTX_EN is high, JAM pattern (55) is transmitted. ISOLATE I Isolate. When this signal is high, the macrocell will come out of reset in isolate mode per the IEEE standard. If this is low, then the macrocell will come out of reset in normal mode. When isolated, all receive outputs are low, and all transmit requests are ignored. While isolated, the macrcell will respond to management transactions, detect, and transmit link pulses. Register 0, bit 10, is used to put the transceiver in/out of isolate mode. APFE_PIN I Autopolarity Function Enable (Active Low). When this signal is set low and the DNC3X3625 is operating at 10 Mbits/s, the autopolarity function will determine if the TP link is wired with a polarity reversal: s The DNC3X3625 will assert the autopolarity status (APS) bit (register 28, bit 6) and correct the polarity reversal. s If this signal is set high and the DNC3X3625 is operating at 10 Mbits/s, the reversal will not be corrected. ELLE_PIN I Extended Line Length Enable. When this signal is set high, the receive squelch level is reduced from a nominal 435 mV to 350 mV, allowing recep- tion of signals with lower amplitude. This is the same function as register 30, bit 4. The input and the register bit are ORed together. HBT_PIN I Heartbeat Enable. When asserted high, this input will enable the heartbeat function (serial mode). This is the same function as register 30, bit 5. The input and the register bit are ORed together. LPBK_PIN I Loopback. When this signal is asserted high DNC3X3125 is in loopback mode. No data transmission will take place on the media and any receive data will be ignored. This is the same function as register 0, bit 14. The input and the register bit are ORed together. NOLP_PIN I No Link Pulse Mode. Setting this signal high will allow 10 Mbits/s operation with link pulses disabled. If the DNC3X3125 is configured for 100 Mbits/s operation, this signal is ignored. This is the same function as register 30, bit 0. The input and the register bit are ORed together. LED_STR_EN I LED Stretch Enable. This pin when low, disables stretching. When high, the LED output is stretched to 42 ms minimum, unless LED_BLINK_EN is high. This signal is ORed with register 29, bit 7. LED_BLINK_EN I LED Blink Enable. This pin when low, disables blinking. When high, the LED output will blink high for 42 ms and low for 42 mS whenever there is activity, unless LED_STR_EN is high, in which case the blinking is 0.5 seconds high and 0.5 seconds low. This signal is ORed with register 29, bit 11. OUI[24:3] I Organizationally Unique Identifier. This can be programmed by the user, upon instantiation of the macro. MODEL[5:0] I Model Number. 6-bit model number of the device. This can be programmed upon instantiation. VERSION[3:0] I Revision Number. The value of the present revision number. This can be programmed upon instantiation. PWRDN I Powerdown. When high, this signal powers down the PHY. Signal Type Description Signal Information (continued) Table 6. Control/Status Signals (continued) |
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