Aeroflex Circuit Technology

SCDCT1995 REV A 11/21/01 Plainview NY (516) 694-6700

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It should be noted that the RT expects the Vector word contents to be already prepared in a latch ready for enabling

onto the internal highway when VECTEN goes low. If the subsystem has not been designed to handle the Vector word

mode command, it will be the fault of the Bus Controller if the RT receives such a command. Since the subsystem is

not required to acknowledge the mode command, the RT will not be affected in any way by Vector word circuitry not

being implemented in the subsystem. It will however transmit a data word as the Vector word, but this word will have no

meaning.

Reset Mode Command

Figure 8 shows the relevant signal timings for an RT receiving a valid reset mode command. Once the command word

has been fully validated and serviced, the RESET signal is pulsed low. This signal may be used as a reset function for

subsystem interface circuitry.

Dynamic Bus Allocation

This mode command is intended for use with a terminal which has the capability of configuring itself into a bus

controller on command from the bus. The line DBCREQ cannot go true unless the DBCACC line was true at the time of

the valid command, i.e. tied low. For terminals acting only as RTs, the signal DBCACC should be tied high (inactive),

and the signal DBCREQ should be ignored and left unconnected.

Use of the Busy Status Bit

The Busy Bit is used by the subsystem to indicate that it is not ready to handle data transfers either to or from the RT.

The RT sets the bit to logic one if the BUSY line from the subsystem is active low at the time of the second falling edge

of INCLK after INCMD goes low. This is shown in Figure 13. Once the Busy bit is set, the RT will stop all receive and

transmit data word transfers to and from the subsystem. The data transfers in the Synchronize with data word and

Transmit Vector word mode commands are not affected by the Busy bit and will take place even if it has been set.

It should be noted that a minimum of 0.5 µs subaddress decoding time is given to the subsystem before setting of

status bits. This allows the subsystem to selectively set the Busy bit if for instance one subaddress is busy but others

are ready. This option will prove useful when an RT is interfacing with multiple subsystems.

Use of the Service Request Status Bit

The Service Request bit is used by the subsystem to indicate to the Bus Controller that an asynchronous service is

requested.

The timing of the setting of this bit is the same as the Busy bit and is shown in Figure 13. Use of SERVREQ has no

effect on the RT apart from setting the Service Request bit.

It should be noted that certain mode commands require that the last status word be transmitted by the RT instead of

the current one, and therefore a currently set status bit will not be seen by the Bus Controller. Therefore the user is

advised to hold SERVREQ low until the requested service takes place.

Use of the Subsystem Status Bit

This status bit is used by the RT to indicate a subsystem fault condition. If the subsystem sets SSERR low at any time,

the subsystem fault condition in the RT will be set, and the Subsystem Flag status bit will subsequently be set. The fault

condition will also be set if a handshaking failure takes place during a data transfer to or from the subsystem. The fault

condition is cleared on power-up or by a Reset mode command.

Dynamic Bus Control Acceptance Status Bit

DBCACC, when set true, enables an RT to configure itself into a Bus Controller, if the subsystem has the capability, by

allowing DBCREQ to pulse true and BIT TIME 18 to be set in the status response. If Dynamic Bus Control is not

required then DBCACC must be tied high. DBCACC tied high inhibits DBCREQ and clears BIT TIME 18 in the status

response.

Bus Driver/Receiver Interface

Receive Data

The decoder chip requires two TTL signals, RXDATA and RXDATA, to represent the data coming in from the bus. PDIN

should be driven to a logic level ‘1’ when the bus waveform exceeds a specified positive threshold and NDIN should be

driven to a logic level ‘1’ when a specified negative threshold is exceeded. During the quiet period on the bus both

signals should be at the same logic level. All the bus receivers must be permanently enabled, the selection of the bus in

use is controlled within the ASIC.