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AD3R1600W8G11

DDR3-1600(CL11) 240-Pin R-DIMM

8GB(1024M x 72-bits)

Pin Description：

PIN

NAME

FUNCTION

CK0~CK1,

/CK0~/CK1

System Clock

Active on the positive and negative edge to sample all inputs.

CKE0~CKE1

Clock Enable

Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at

least on cycle prior new command. Disable input buffers for power down in standby

/S0~/S1

Chip Select

Disables or Enables device operation by masking or enabling all input except CK, CKE and

L(U)DQM

A0~A14

Address

Row / Column address are multiplexed on the same pins.

(Row Address: A0~A14 , Column Address: A0~A9 , Auto precharge: A10/AP)

BA0~BA2

Banks Select

Selects bank to be activated during row address latch time.

Selects bank for read / write during column address latch time.

DQ0~DQ63

CB0~CB7

Data

Data and check bit inputs / outputs are multiplexed on the same pins.

DQS0~DQS8,

/DQS0~/DQS8

Data Strobe

Bi-directional Data Strobe

DM0~DM8

Data Mask

Mask input data when DM is high.

/RAS

Row Address Strobe

Latches row addresses on the positive edge of the CK with /RAS low

/CAS

Column Address Strobe Latches Column addresses on the positive edge of the CK with /CAS low

/WE

Write Enable

Enables write operation and row recharge.

VDD / VSS

Power Supply/Ground

Power and Ground for the input buffers and the core logic.

VREFDQ

Power Supply reference Power Supply for reference.DQ,DM.VDD/2

VREFCA

Power Supply reference Power Supply for reference. Command , address, & control.VDD/2

VDDQ

Power Supply

Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity

SDA

Serial data I/O

EEPROM serial data I/O