SSM2402/SSM2412

REV. A

–8–

When the Ramp Output reaches +3 V, and the drive for the

Main Switch Control output is gated OFF by differential ampli-

followers provide essentially zero gate-to-source voltage over the

full audio signal range; this in turn assures a constant low im-

pedance in the ON state over the full audio signal range. Total

time to turn on the SSM2402 switch is approximately 10.0 ms

and 3.5 ms for the SSM2412.

In systems using a large number of separate switches, there are

advantages to having faster switching into OFF state than into

the ON state. Break-before-make can be maintained at the sys-

tem level. To see how the SSM2402/SSM2412 guarantee

break-before-make, consider the ON-to-OFF transition.

A Control Input LOW initiates the ON-to-OFF transition. The

Ramp Generator integrates down from approximately +7 V to-

wards –7 V. As the ramp goes through +3 V, the comparator

the OFF state. At this time, all switches in the “T” are OFF.

When the ramp integrates down to –3 V, the Shunt Switch Con-

only the time interval required for the ramp to go from +7 V to

+3 V, about 4 ms for the SSM2402, and 1.5 ms for the

SSM2412. The time to turn on is about 2.5 times as long as the

time to turn off.

Typical Configuration

The SSM2402/SSM2412 are much more than simple single

solid state switches. The “T” configuration provides superb

OFF-isolation through shunting of feedthrough via shunt switch

vides a controlled gating action that softens the ON/OFF transi-

tions. Distortion is minimized by holding zero gate-to-source

op amp followers. Figure 3 shows a distortion comparison be-

tween the SSM2402 and a typical CMOS switch. In summary,

the SSM2402/SSM2412 are designed specifically for high per-

formance audio system usage.

OVERVOLTAGE PROTECTION

The SSM2402/SSM2412 are designed to guarantee correct op-

eration with inputs of up to

±14.2 V with ±18 V supplies. The

switch input should never be forced to go beyond the supply

rails. In the OFF condition, if the inputs exceeds +14.2 V,

there is a risk of turning the respective input pass FET “ON.”

When the input voltage rises to within 3.8 V of the positive

supply, the op amp follower saturates and will not be able to

maintain the full 2.5 V of back bias on the gate-to-source

junction. Under this condition, current will flow from the input

through the shunt FET to the negative supply. This current is

rent will not damage the device, there is a danger of also turn-

ing on the output pass FET, especially if the output is close to

the negative rail.

This risk of signal “breakthrough” for inputs above +14.2 V can

be eliminated by using a source resistor of 100

Ω–500 Ω in series

with the analog input to provide additional current limiting.

can no longer keep the switch OFF. Signal breakthrough can-

not happen, but the danger here is latch-up via a path to V–

through the shunt FET. Additional circuitry (not shown) has

been incorporated to turn OFF the shunt FET under these

conditions, and the potential for latch-up is thereby eliminated.

Figure 3. Comparison of the SSM2402 and

Typical CMOS Switch for Distortion