REV PrK

–3–

EVAL-AD766XCB/AD767XCB

PRELIMINARY TECHNICAL DATA

TABLE II. JUMPER DESCRIPTION

Jumper

Default position

Function

Designation with the control

board ( Factory

settings)

Figure 10 is the FFT Screen, which performs an FFT on the

captured data, computes the Signal-to-Noise Ratio (SNR),

Signal-to-Noise-plus-Distortion (SINAD) and total-Har-

monic-Distortion (THD). Figure 11 is the time domain

representation of the output. When the on-board

CNVST

generation is used, a synchronous FFT could be achieved by

synchronizing the external AC generator with the Fsync signal

(TP11) which is an exact division by 2 of MCLK.

Software Installation

- Double-Click on Setup.exe from the CD-ROM and follow the

installation instructions.

NOTE: The software runs under Windows 95/98 only.

JP1

A

Selection of the positive supply of the front-end amplifier U6. When JP1 is in posi-

tion A, the +12V supply from the control board is applied to JP3 otherwise VS+ on

SJ3 is used.

JP2

A

Selection of the negative supply of the front-end amplifier U6. When JP2 is in posi-

tion A, the -12V supply from the control board is applied to JP4 otherwise VS- on

SJ3 is used.

JP3

A

Selection of the positive supply of the front-end amplifier U6. When JP3 is in posi-

tion A, the +5V supply from the control board is used otherwise JP1 output is used.

JP4

A

Selection of the negative supply of the front-end amplifier U6. When JP4 is in posi-

tion A, the -5V supply from the control board is used otherwise JP2 output is used.

JP5

not A

Selection of the master clock MCLK signal. When JP5 is in position A, the signal on

J4 is used otherwise the on-board 20 MHz clock is used as a MCLK signal. MCLK

signal is used to generate the on-board

CNVST signal and the external serial clock

SCLK.

JP6

A, U3 side

Selection of RDC ( Read during convert ). When the button of the switch is close to

J4 connector ( not A position ) and when the serial reading mode is selected, the data

are read during conversion otherwise the data are read after conversion. JP6 has no

use in parallel reading mode.

JP7

A, U3 side

Selection of PD ( Powerdown ). When the button of the switch is close to J4 connec-

tor ( not A position ), the ADC is in power-down mode.

JP8

A, U3 side

Spare switch.

JP9

A, U3 side

Selection of RESET. When the button of the switch is close to J4 connector ( not A

position ), the ADC is reset.

JP10

A, U3 side

Selection of SER/

PAR ( serial/parallel reading mode ). When the button of the switch

is close to J4 connector ( not A position ), the data are read in serial mode otherwise

the data are read in parallel mode.

JP11

not A, SJ4 side

Selection of OC/

2C ( coding ). When the button of the switch is close to J4 connector

( not A position ), the ADC uses a straight binary coding otherwise the twos comple-

ment coding is used.

JP12

A, U3 side

Selection of WARP. When the button of the switch is close to J4 connector ( not A

position ), the ADC uses the WARP mode which is the fastest one. With the AD7660,

JP12 is a spare switch.