IMAGE

SENSOR

1080p60

SN65LVDS324

SD[1:0]P/N

SD[4:3]P/N

SCLKP/N

SD2P/N

SD[11:5]P/N

SCL

SDA

1.8V

VCC

VCCA

CLKIN

CH1[1:0]_P/N

CH2[1:0]_P/N

CLK1_P/N

CLK2_P/N

Configuration

and Control

CSR 09[2:0] = 3’b010

CSR 0A[1:0] = 2’b10

Digital Signal

Processor

D[15:12]

D[11:0]

CLKOUT

VSYNC

HSYNC

CLKOUT = 148.5MHz

D[15:12] Output = 4’b0

DSP I/O @ 1.8V CMOS

NC

1.8V

< 1cm difference in length

RST

1.5k Ω

2-Channel 2-Port

12-Bit 1080p60

LVDS DDR @ 222.75MHz

37.125 MHz

IMAGE

SENSOR

1080p60

Digital Signal

Processor

RST

D[15:12]

D[11:0]

CLKOUT

VSYNC

HSYNC

< 1cm difference in length

SN65LVDS324

SD[11:0]P

SD[11:0]N

SCLKP/N

SD[1:0]P/N

SCL

SDA

1.8V

VCC

VCCA

37.125 MHz

LVDS Parallel 12-Bit 1080p60

LVDS DDR @ 74.25MHz

D[11:0]_P

D[11:0]_N

CLK_P/N

3x 10 Ω

CLKOUT = 148.5MHz

D[15:12] Output = 4’b0

DSP I/O @ 1.8V CMOS

NC

1.8V

1.5kΩ

Configuration and Control

CSR 09[2:0] = 3’b001

CSR 0A[1:0] = 2’b10

SN65LVDS324

SLLSED9 – NOVEMBER 2012

www.ti.com

TYPICAL APPLICATIONS (continued)

Sony LVDS Parallel 12-Bit Mode

Figure 14 illustrates the 12-bit LVDS Parallel mode for 1080p60 operation. This mode operates identically to the

LVDS Parallel 10-bit mode other than the data width and sync codes.

Figure 14. LVDS Parallel 12bpp Application

Panasonic 2-Channel 2-Port 12-Bit Mode

Figure 15 illustrates the 1080p60 2-Channel 2-Port 12-bit operating mode.

Figure 15. 2-Channel 2-Port 12bpp Application

The channel 2 clock is not guaranteed to be synchronous with channel 1; the SN65LVDS324 Word Alignment

function provides the data synchronization between channel 1 and channel 2. If the sensor output is dual-frame

WDR, the SN65LVDS324 transmits the data for both frames.

16

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