SN65DSI85

SLLSEB9C – SEPTEMBER 2012 – REVISED DECEMBER 2012

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SWITCHING CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

DSI

DSI LP glitch suppression pulse width

300

ps

Skew time from DSI Channel A to Channel B in dual DSI

See Figure 20

operation

LVDS

Output clock period

6.49

40

ns

High-level output clock (CLK) pulse duration

ns

Delay time, CLK

↑ to 1st serial bit position

-0.15

0.15

ns

Delay time, CLK

↑ to 2nd serial bit position

ns

Delay time, CLK

↑ to 3rd serial bit position

ns

Delay time, CLK

↑ to 4th serial bit position

Input clock jitter < 25 ps

ns

(REFCLK)

Delay time, CLK

↑ to 5th serial bit position

ns

Delay time, CLK

↑ to 6th serial bit position

ns

Delay time, CLK

↑ to 7th serial bit position

ns

Differential output rise-time

see Figure 4

180

500

ps

Differential output fall-time

EN, ULPS, RESET

Enable time from EN or ULPS

1

ms

Disable time to standby; see Figure 5

0.1

Reset Time

10

ms

REFCLK

REFCLK Freqeuncy. Supported frequencies:

25

154

MHz

25 MHz - 15 4MHz

REFCLK rise and fall time

100ps

1ns

s

REFCLK Peak-to-Peak Phase Jitter

50

ps

Duty

REFCLK Duty Cycle

40%

50%

60%

REFCLK or DSI CLK (DACP/N, DBCP/N)

0.5%

1%

2%

SSC_CLKIN

Modulation Frequency Range

30

60

kHz

(1)

(2)

For EMI reduction purpose, SN65DSI85 supports the center spreading of the LVDS CLK output through the REFCLK or DSI CLK input.

The center spread CLK input to the REFCLK or DSI CLK is passed through to the LVDS CLK output A_CLKP/N and/or B_CLKP/N.

Figure 1. DSI HS Mode Receiver Timing Definitions

8

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