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SN65DSI85 Datasheet(PDF) 8 Page - Texas Instruments |
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SN65DSI85 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 45 page SN65DSI85 SLLSEB9C – SEPTEMBER 2012 – REVISED DECEMBER 2012 www.ti.com SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT DSI tGS DSI LP glitch suppression pulse width 300 ps Skew time from DSI Channel A to Channel B in dual DSI tSK See Figure 20 operation LVDS tc Output clock period 6.49 40 ns tw High-level output clock (CLK) pulse duration 4/7 tc ns t0 Delay time, CLK ↑ to 1st serial bit position -0.15 0.15 ns t1 Delay time, CLK ↑ to 2nd serial bit position 1/7 tc – 0.15 1/7 tc + 0.15 ns t2 Delay time, CLK ↑ to 3rd serial bit position 2/7 tc – 0.15 2/7 tc + 0.15 ns tc = 6.49 ns; t3 Delay time, CLK ↑ to 4th serial bit position Input clock jitter < 25 ps 3/7 tc – 0.15 3/7 tc + 0.15 ns (REFCLK) t4 Delay time, CLK ↑ to 5th serial bit position 4/7 tc – 0.15 4/7 tc + 0.15 ns t5 Delay time, CLK ↑ to 6th serial bit position 5/7 tc – 0.15 5/7 tc + 0.15 ns t6 Delay time, CLK ↑ to 7th serial bit position 6/7 tc – 0.15 6/7 tc + 0.15 ns tr Differential output rise-time see Figure 4 180 500 ps tf Differential output fall-time EN, ULPS, RESET ten Enable time from EN or ULPS 1 tc(o) = 12.9 ns ms tdis Disable time to standby; see Figure 5 0.1 treset Reset Time 10 ms REFCLK REFCLK Freqeuncy. Supported frequencies: FREFCLK 25 154 MHz 25 MHz - 15 4MHz tr, tf REFCLK rise and fall time 100ps 1ns s tpj REFCLK Peak-to-Peak Phase Jitter 50 ps Duty REFCLK Duty Cycle 40% 50% 60% REFCLK or DSI CLK (DACP/N, DBCP/N) SSC enabled Input CLK center spread depth(2) 0.5% 1% 2% SSC_CLKIN Modulation Frequency Range 30 60 kHz (1) All typical values are at VCC = 1.8 V and TA = 25°C (2) For EMI reduction purpose, SN65DSI85 supports the center spreading of the LVDS CLK output through the REFCLK or DSI CLK input. The center spread CLK input to the REFCLK or DSI CLK is passed through to the LVDS CLK output A_CLKP/N and/or B_CLKP/N. Figure 1. DSI HS Mode Receiver Timing Definitions 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: SN65DSI85 |
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