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ADS54T02 Datasheet(PDF) 26 Page - Texas Instruments |
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ADS54T02 Datasheet(HTML) 26 Page - Texas Instruments |
26 / 43 page DA[11..0] TRIGGER Low Resolution 2 13 samples Ready for new trigger Trigger on rising edge of TRIGGER TRDY High-Resolution 2 10 samples tTRIG_DELAY HRES Low Resolution 2 (N+3) samples Ready for new trigger High-Resolution 2 N samples Update value N Enable Burst Mode Manual Trigger ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com Manual Trigger Mode The control of the high resolution output is shown below along with the two output flags (TRDY and HRES). Figure 38. Triggering High Resolution Mode and Lockout Time After enabling burst mode, the output data DA[11..0] are forced to low resolution mode for 213 samples. During that period any trigger signal is ignored. The completion of the low resolution sample cycle is signaled by a logic high on the TRDY output pins indicating that a high resolution (12-bit) data output burst can be triggered by a low to high transition on the TRIGGER input. The ADC monitors the TRIGGER input at each rising edge of the input clock. The high resolution output data starts with a delay of tTRIG_DELAY = 1-2 DACLK clock cycles and is indicated through the HRES data flag which stays high for all 2N high resolution samples. At completion the register value for N is verified and transmission of 2(N+3) low resolution data immediately follows. Once the last low resolution sample is output on the output data bus, the flag TRDY is asserted high again indicating the end of the lockout period and the next 2N high resolution samples can be triggered again. Auto Trigger Mode This mode is enabled by setting the auto trigger bit via SPI register write and the DA data outputs start in low resolution for 213 samples. Immediately following completion of transmission of the last low resolution sample, the outputs automatically start transmitting 210 high resolution samples without the need for external trigger ensuring maximum efficiency. Any input signal on the TRIGGER pins is ignored and the TRDY flag will go high only for one clock cycle with the start of the high resolution data. The output flag HRES is aligned with the 2N high resolution output samples and the parameter N can be changed until the next output cycle starts again with low resolution output data. 26 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 |
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