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RT8016-18PQW Datasheet(PDF) 10 Page - Richtek Technology Corporation |
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RT8016-18PQW Datasheet(HTML) 10 Page - Richtek Technology Corporation |
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10 / 13 page  RT8016L 10 DS8016L-02 March 2011 www.richtek.com looking into the LX pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows : RSW = RDS(ON)TOP x DC + RDS(ON)BOT x (1−DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Operating Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD (ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady state value. During this recovery time, VOUT can be monitored for overshoot or ringing which would indicate a stability problem. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications of the RT8016L, the maximum junction temperature is 125 °C and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN- 8L 1.6x1.6 (COL) packages, the thermal resistance, θJA, is 120 °C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25 °C can be calculated by the following formula: PD(MAX) = (125 °C − 25°C) / (120°C/W) = 0.833W for WQFN-8L 1.6x1.6 (COL) package The maximum power dissipation depends on the operating ambient temperature for fixed TJ (MAX) and thermal resistance, θJA. For the RT8016L package, the derating curve in Figure 4 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Layout Considerations Follow the PCB layout guidelines for optimal performance of the RT8016L. For the main current paths, keep their traces short and wide. Put the input capacitor as close as possible to the device pins (VIN and GND). LX node is with high frequency voltage swing and should be kept in a small area. Keep analog components away from LX node to prevent stray capacitive noise pick-up. Connect feedback network behind the output capacitors. Keep the loop area small. Place the feedback components near the RT8016L. Connect all analog grounds to a common node and then connect the common node to the power ground behind the output capacitors. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 25 50 75 100 125 Ambient Temperature (°C) Four Layer PCB ( °C) Figure 4 |
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