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ADV7197 Datasheet(PDF) 10 Page - Analog Devices |
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ADV7197 Datasheet(HTML) 10 Page - Analog Devices |
10 / 20 page REV. 0 ADV7197 –10– FUNCTIONAL DESCRIPTION Digital Inputs The digital inputs of the ADV7197 are TTL-compatible. 30-bit YCrCb or RGB pixel data in 4:4:4 format or 20-bit YCrCb pixel data in 4:2:2 format is latched into the device on the rising edge of each clock cycle at 74.25 MHz or 74.1758 in HDTV mode. It is recommended to input data in 4:2:2 mode to make use of the Chroma SSAFs on the ADV7197. As can be seen in the figures below, these filters have 0 dB passband response and prevent signal components being folded back into the frequency band. In 4:4:4 input mode, the video data is already interpo- lated by an external input device and the chroma SSAFs of the ADV7197 are bypassed. RBW 10kHz VBW 300Hz SWP 17.0SEC START 100kHz STOP 20.00MHz RL –10.0dBm 10dB/ 3.18MHz ATTEN 10dB VAVG 1 MKR 0dB Figure 6. SSAF Response to a 2.5 MHz Chroma Sweep Using 4:2:2 Input Mode RBW 10kHz VBW 300Hz SWP 17.0SEC START 100kHz STOP 20.00MHz RL –10.0dBm 10dB/ 3.12MHz ATTEN 10dB VAVG 4 MKR –3.00dB Figure 7. Conventional Filter Response to a 2.5 MHz Chroma Sweep Using 4:4:4 Input Mode Control Signals The ADV7197 accepts sync control signals accompanied by valid 4:2:2 or 4:4:4 data. These external horizontal, vertical and blanking pulses (or EAV/SAV codes) control the insertion of appropriate sync information into the output signals. Analog Outputs The analog Y signal is output on the 11-bit + Sync DAC A, the color component analog signals on the 11-bit DACs B, C conforming to EIA-770.3 standards RSET has a value of 2470 Ω (EIA-770.3), RLOAD has a value of 300 Ω. For the outputs to con- form to RS-170/RS-343A standards RSET must have a value of 2820 Ω. Internal Test Pattern Generator The ADV7197 can generate a Cross-Hatch pattern (white lines against a black background). Additionally, the ADV7197 can output a uniform color pattern. The color of the lines or uni- form field/frame can be programmed by the user. Y/CrCb Delay The Y output and the color component outputs can be delayed wrt the falling edge of the horizontal sync signal by up to four clock cycles. I 2C Filter A selectable internal I 2C filter allows significant noise reduction on the I 2C interface. For setting ALSB high, the input band- width on the I 2C lines is reduced and pulses of less than 50 ns are not passed to the I 2C controller. Setting ALSB low allows greater input bandwidth on the I 2C lines. MPU PORT DESCRIPTION The ADV7197 support a 2-wire serial (I 2C-compatible) micro- processor bus driving multiple peripherals. Two inputs Serial Data (SDA) and Serial Clock (SCL) carry information between any device connected to the bus. Each slave device is recognized by a unique address. The ADV7197 has four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 8. The LSB sets either a read or write operation. Logic Level “1” corresponds to a read operation while Logic Level “0” corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7197 to Logic Level “0” or Logic Level “1.” When ALSB is set to “0,” there is greater input bandwidth on the I 2C lines, which allows high-speed data transfers on this bus. When ALSB is set to “1,” there is reduced input bandwidth on the I 2C lines, which means that pulses of less than 50 ns will not pass into the I 2C internal controller. This mode is recommended for noisy systems. 0 X 1 0 1 01 A1 READ/WRITE CONTROL 0 WRITE 1READ ADDRESS CONTROL SET UP BY ALSB Figure 8. Slave Address To control the various devices on the bus the following protocol must be followed. First the master initiates a data transfer by establishing a Start condition, defined by a high-to-low transi- tion on SDA while SCL remains high. This indicates that an address/data stream will follow. All peripherals respond to the Start condition and shift the next eight bits (7-bit address + R/ W bit). The bits are transferred from MSB down to LSB. The periph- eral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an Acknowledge Bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCL lines waiting for the Start condition and the correct transmitted address. The R/ W bit determines the direction of the data. |
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