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ADV7196A Datasheet(PDF) 16 Page - Analog Devices |
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ADV7196A Datasheet(HTML) 16 Page - Analog Devices |
16 / 36 page REV. 0 ADV7196A –16– VBI Open (MR14) This bit enables or disables the facility of VBI data insertion during the Vertical Blanking Interval. For this purpose Lines 13 to 42 of each frame can be used for VBI when SMPTE293M standard is used, or Lines 6 to 43 when ITU-R.BT1358 standard is used. Undershoot Limiter (MR15–MR16) This control limits the Y signal to a programmable level in the active video region. Available limit levels are –1.5 IRE, –6 IRE, –11 IRE. Note that this facility is only available when Interpolation is enabled (MR36 = “1”). Sharpness Filter (MR17) This control bit enables or disables the Sharpness Filter mode. This bit must be set to “1” for any values programmed into the Filter Gain 1 Register to take effect. It must also be set to “1” when Adaptive Filter mode is used. Refer to Sharpness Filter control and Adaptive Filter control section. –6IRE 100IRE 0IRE –40IRE Figure 19. Undershoot Limiter, Programmed to –6 IRE MODE REGISTER 1 MR1 (MR17–MR10) (Address (SR4–SR0) = 01H) Figure 20 shows the various operations under the control of Mode Register 1. MR1 BIT DESCRIPTION Pixel Data Enable (MR10) When this bit is set to “0,” the pixel data input to the ADV7196A is blanked such that a black screen is output from the DACs. When this bit is set to “1,” pixel data is accepted at the input pins and the ADV7196A outputs the standard set in “Output Standard Selection” (MR01–00). This bit must be set to “1” to enable out- put of the test pattern signals. Input Format (MR11) It is possible to input data in 4:2:2 format or at 4:4:4 format at 27 MHz. Test Pattern Enable (MR12) Enables or disables the internal test pattern generator. Test Pattern Hatch/Frame (MR13) If this bit is set to “0,” a cross-hatch test pattern is output from the ADV7196A (for example, in SMPTE293M 11 horizontal and 11 vertical white lines, four pixels wide are displayed against a black background). The cross-hatch test pattern can be used to test monitor convergence. If this bit is set to “1,” a uniform colored frame/field test pattern is output from the ADV7196A. The color of the lines or the frame/field is by default white but can be programmed to be any color using the Color Y, Color Cr, Color Cb registers. MR11 MR17 MR12 MR14 MR15 MR16 MR17 0 DISABLED 1 ENABLED SHARPNESS FILTER MR13 MR10 MR14 0 DISABLED 1 ENABLED VBI OPEN MR12 0 DISABLED 1 ENABLED TEST PATTERN ENABLE MR10 0 DISABLED 1 ENABLED PIXEL DATA ENABLE MR16 MR15 0 0 DISABLED 01 –11IRE 10 –6IRE 11 –1.5IRE UNDERSHOOT LIMITER MR13 0HATCH 1 FIELD/FRAME TEST PATTERN HATCH/FRAME MR11 0 4:4:4 YCRCB 1 4:2:2 YCRCB INPUT FORMAT Figure 20. Mode Register 1 |
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