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ADV7175A Datasheet(PDF) 26 Page - Analog Devices |
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ADV7175A Datasheet(HTML) 26 Page - Analog Devices |
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26 / 52 page  ADV7175A/ADV7176A –26– REV. B Genlock Control (MR22–MR21) These bits control the genlock feature of the ADV7175A/ ADV7176A. Setting MR21 to a Logic “1” configures the SCRESET/RTC pin as an input. Setting MR22 to Logic Level “0” configures the SCRESET/RTC pin as a subcarrier reset input, therefore, the subcarrier will reset to Field 0, following a high-to-low transition on the SCRESET/RTC pin. Setting MR22 to Logic Level “1” configures the SCRESET/RTC pin as a real-time control input. Active Video Line Control (MR23) This bit switches between two active video line durations. A zero selects ITU-R BT.470 (720 pixels PAL/NTSC) and a one selects ITU-R/SMPTE “analog” standard for active video dura- tion (710 pixels NTSC 702 pixels PAL). Chrominance Control (MR24) This bit enables the color information to be switched on and off the video output. Burst Control (MR25) This bit enables the burst information to be switched on and off the video output. RGB/YUV Control (MR26) This bit enables the output from the RGB DACs to be set to YUV output video standard. Bit MR06 of Mode Register 0 must be set to Logic Level “1” before MR26 is set. Lower Power Control (MR27) This bit enables the lower power mode of the ADV7175A/ ADV7176A. This will reduce the DAC current by 50%. NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0 (PCE15–0, PCO15–0)/ (TXE15–0, TXO15–0) (Subaddress [SR4–SR0] = 11–0EH) These 8-bit wide registers are used to set up the NTSC pedes- tal/PAL teletext on a line-by-line basis in the vertical blanking interval for both odd and even fields. Figures 40 and 41 show the four control registers. A Logic “1” in any of the bits of these registers has the effect of turning the pedestal OFF on the equivalent line when used in NTSC. A Logic “1” in any of the bits of these registers has the effect of turning teletext ON the equivalent line when used in PAL. FIELD 1/3 PCO6 PCO5 PCO3 PCO1 PCO4 PCO2 PCO0 PCO7 LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 PCO14 PCO13 PCO11 PCO9 PCO12 PCO10 PCO8 PCO15 LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 FIELD 1/3 FIELD 2/4 PCE6 PCE5 PCE3 PCE1 PCE4 PCE2 PCE0 PCE7 LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 PCE14 PCE13 PCE11 PCE9 PCE12 PCE10 PCE8 PCE15 LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 FIELD 2/4 Figure 40. Pedestal Control Registers FIELD 1/3 FIELD 1/3 FIELD 2/4 FIELD 2/4 TXO6 TXO5 TXO3 TXO1 TXO4 TXO2 TXO0 TXO7 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7 TXO14 TXO13 TXO11 TXO9 TXO12 TXO10 TXO8 TXO15 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15 TXE6 TXE5 TXE3 TXE1 TXE4 TXE2 TXE0 TXE7 TXE14 TXE13 TXE11 TXE9 TXE12 TXE10 TXE8 TXE15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15 Figure 41. Teletext Control Registers MODE REGISTER 3 MR3 (MR37–MR30) (Address [SR4–SR0] = 12H) Mode Register 3 is an 8-bit wide register. Figure 42 shows the various operations under the control of Mode Register 3. MR3 BIT DESCRIPTION Revision Code (MR30) This bit is read only and indicates the revision of the device. VBI Pass-Through Control (MR31) This bit determines whether or not data in the vertical blanking interval (VBI) is output to the analog outputs or blanked. Reserved (MR33–MR32) These bits are reserved. Teletext Enable (MR34) This bit must be set to “1” to enable teletext data insertion on the TTX pin. MR21 MR27 MR22 MR23 MR26 MR25 MR24 MR20 CHROMINANCE CONTROL 0 ENABLE COLOR 1 DISABLE COLOR MR24 GENLOCK SELECTION x 0 DISABLE GENLOCK 0 1 ENABLE SUBCARRIER RESET PIN 1 1 ENABLE RTC PIN MR22 MR21 RGB/YUV CONTROL 0 RGB OUTPUT 1 YUV OUTPUT MR26 SQUARE PIXEL CONTROL 0 DISABLE 1 ENABLE MR20 BURST CONTROL 0 ENABLE BURST 1 DISABLE BURST MR25 LOWER POWER MODE 0 DISABLE 1 ENABLE MR27 ACTIVE VIDEO LINE WIDTH CONTROL 0 720 PIXELS ACTIVE LINE 1 ITU-R/SMPTE ACTIVE LINE MR23 Figure 39. Mode Register 2 |
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