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ADV473 Datasheet(PDF) 3 Page - Analog Devices

Part No. ADV473
Description  CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADV473 Datasheet(HTML) 3 Page - Analog Devices

 
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ADV473
–3–
REV. A
TIMING CHARACTERISTICS1
(VAA
2 = 5 V; V
REF = 1.235 V; RL = 37.5
Ω, C
L = 10 pF; RSET = 140
Ω.
All specifications TMIN to TMAX
3 unless otherwise noted.)
135 MHz
110 MHz
80 MHz
66 MHz
Parameter
Version
Version
Version
Version
Units
Conditions/Comments
fmax
135
110
80
66
MHz
Clock Rate
t1
10
10
10
10
ns min
RS0–RS2 Setup Time
t2
10
10
10
10
ns min
RS0–RS2 Hold Time
t3
4
3
3
3
3
ns min
RD
Asserted to Data Bus Driven
t4
4
40
40
40
40
ns max
RD
Asserted to Data Valid
t5
5
20
20
20
20
ns max
RD
Negated to Data Bus 3-Stated
t6
5
5
5
5
5
ns min
Read Data Hold Time
t7
10
10
10
10
ns min
Write Data Setup Time
t8
10
10
10
10
ns min
Write Data Hold Time
t9
100
100
100
100
ns max
CR0–CR3 Delay Time
t10
50
50
50
50
ns min
RD
, WR Pulse Width Low
t11
40
40
40
40
ns min
RD
, WR Pulse Width High
t12
2
3
3
3
ns min
Pixel & Control Setup Time
t13
2
3
3
3
ns min
Pixel & Control Hold Time
t14
7.4
9.1
12.5
15.15
ns min
Clock Cycle Time
t15
3
3.5
4
5
ns min
Clock Pulse Width High Time
t16
2
3
4
5
ns min
Clock Pulse Width Low Time
t17
30
30
30
30
ns max
Analog Output Delay
t18
3
3
3
3
ns typ
Analog Output Rise/Fall Time
t19
6
13
13
13
13
ns max
Analog Output Settling Time
tSK
2
2
2
2
ns max
Analog Output Skew
tPD
4
× t
14
4
× t
14
4
× t
14
4
× t
14
ns
Pipeline Delay
NOTES
1TTL input values are 0 to 3 volts, with input rise/fall times
≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load
≤ 10 pF, D0-D7 output load ≤ 50 pF. See timing notes in Figure 2.
2V
AA = 5 V ± 5%.
3Temperature range (T
MIN to TMAX); 0°C to +70°C; TJ (Silicon Junction Temperature) ≤ 100°C .
4t
3 and t4 are measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.4 V or 2.4 V.
5t
5 and t6 are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 3. The measured number is
then extrapolated back to remove the effects of charging the 50 pF capacitor. This means that the times, t 5 and t6, quoted in the timing characteristics are the
true values for the device and, as such, are independent of external bus loading capacitances.
6Settling time does not include clock and data feedthrough.
Specifications subject to change without notice.
RS0, RS1,
RS2
D0–D7
(READ)
D0–D7
(WRITE)
RD, WR
DATA OUT (RD = 0)
DATA IN (WR = 0)
VALID
CR0–CR3
t
4
t
3
t
1
t
2
t
10
t
5
t
11
t
6
t
8
t
7
t
9
Figure 1. MPU Read/Write Timing
DATA
IOR, IOG, IOB
NOTES
1. OUTPUT DELAY MEASURED FROM THE 50% POINT OF THE RISING EDGE
OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. SETTLING TIME MEASURED FROM THE 50% POINT OF FULL-SCALE
TRANSITION TO THE OUTPUT REMAINING WITHIN
±1 LSB.
3. OUTPUT RISE/FALL TIME MEASURED BETWEEN THE 10% AND 90%
POINTS OF FULL-SCALE TRANSITION.
CLOCK
R0-R7, G0–G7,
B0–B7,
OL0-OL3, S0–S1,
SYNC, BLANK
t
14
t
16
t
15
t
12
t
19
t
18
t
13
t
17
Figure 2. Video Input/Output Timing
3.2mA
+2.1V
TO
OUTPUT
PIN
50pF
400
µA
Figure 3. Load Circuit for Bus
Access and Relinquish Time


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