Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

ADV473 Datasheet(PDF) 5 Page - Analog Devices

Part No. ADV473
Description  CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC
Download  12 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo 

ADV473 Datasheet(HTML) 5 Page - Analog Devices

 
Zoom Inzoom in Zoom Outzoom out
 5 / 12 page
background image
ADV473
–5–
REV. A
PIN FUNCTION DESCRIPTION
BLANK
Composite Blank Control Input (TTL Compatible). A logic zero drives the analog outputs to the blanking level.
It is latched on the rising edge of CLOCK. When BLANK is a logical zero, the pixel and overlay inputs are
ignored.
SYNC
Composite SYNC Control Input (TTL Compatible). A logical zero on this input switches off a 40 IRE current
source on the analog outputs. SYNC does not override any other control or data input; therefore, it should be
asserted only during the blanking interval. It is latched on the rising edge of CLOCK. If sync information is not
required on the analog outputs, SYNC should be connected to ground.
CLOCK
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7, S0, S1,
OL0–OL3, SYNC, and BLANK inputs. It is typically the pixel clock rate of the video system. It is
recommended that CLOCK be driven by a dedicated TTL buffer.
R0–R7
Red, Green and Blue Select Inputs (TTL Compatible). These inputs specify, on a pixel basis, the color value to
B0–B7
be written to the DACs. They are latched on the rising edge of CLOCK. R0, G0 and B0 are the LSBs. Unused
G0–G7
inputs should be connected to GND.
S0, S1
Color Mode Select Inputs (TTL Compatible). These inputs specify the mode of operation as shown in Table III.
They are latched on the rising edge of CLOCK.
OL0–OL3
Overlay Select Inputs (TTL Compatible). These inputs specify which palette is to be used to provide color
information. When accessing the overlay palette, the R0–R7, G0–G7, B0–B7, S0 and S1 inputs are ignored. They
are latched on the rising edge of CLOCK. OL0 is the LSB. Unused inputs should be connected to GND.
IOR, IOG, IOB
Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75
Ω coaxial cable.
RSET
Full-Scale Adjust Resistor. A resistor (RSET) connected between this pin and GND controls the magnitude of the
full-scale video signal. The relationship between RSET and the full-scale output current on each output is:
RSET (Ω) = 3,195 × VREF (V)/IOUT (mA) SETUP = 7.5 IRE)
RSET (Ω) = 3,025 × VREF (V)/IOUT (mA) SETUP = 0 IRE)
COMP
Compensation Pin. These pins should be connected together at the chip and connected through 0.1
µF ceramic
capacitor to VAA.
VREFIN
Voltage Reference Input. This input requires a 1.2 V reference voltage. This is achieved through the on-board
voltage reference generator by connecting VREFOUT to VREFIN. If an external reference is used, it must supply
this input with a 1.2 V (typical) reference.
VREFOUT
Voltage Reference Output. This output delivers a 1.2 V reference voltage from the device’s on-board voltage
reference generator. It is normally connected directly to the VREFIN pin. If it is preferred to use an external
voltage reference, this pin may be left floating. Up to four ADV473s can be driven from VREFOUT.
VAA
Analog power. All VAA pins must be connected.
GND
Analog Ground. All GND pins must be connected.
WR
Write Control Input (TTL Compatible). D0–D7 data is latched on the rising edge of WR, and RS0–RS2 are
latched on the falling edge of WR during MPU write operations. RD and WR should not be asserted
simultaneously.
RD
Read Control Input (TTL Compatible). To read data from the device, RD must be a logical zero. RS0–RS2 are
latched on the falling edge of RD during MPU read operations. RD and WR should not be asserted
simultaneously.
RS0, RS1, RS2
Register Select Inputs (TTL Compatible). RS0–RS2 specify the type of read or write operation being performed.
D0–D7
Data Bus (TTL Compatible). Data is transferred into and out of the device over this eight-bit bidirectional data
bus. D0 is the least significant bit.
CR0–CR7
Control Outputs (TTL Compatible). These outputs are used to control application specific features. The output
values are determined by the contents of the command register (CR).


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn