ADV101

–5–

REV. B

PIN FUNCTION DESCRIPTION

Pin

Mnemonic

Function

BLANK

Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs,

IOR, IOB and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While

BLANK

is a logical zero, the R0–R7, G0–G7, R0–R7 and REF WHITE pixel and control inputs are ignored.

SYNC

Composite sync control input (TTL compatible). A logical zero on the SYNC input; switches off a 40 IRE cur-

only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK.

CLOCK

Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7, SYNC,

BLANK

and REF WHITE pixel and control inputs. It is typically the pixel clock rate of the video system.

CLOCK should be driven by a dedicated TTL buffer.

REF WHITE

Reference white control input (TTL compatible). A logical one on this input forces the IOR, IOG and IOB out-

puts to the white level, regardless of the pixel input data (R0–R7, G0–G7 and B0–B7) REF WHITE is latched

on the rising edge of clock.

R0–R7,

Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK. R0,

G0–G7,

G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular

B0–B7

PCB power or ground plane.

IOR, IOG, IOB

Red, green and blue current outputs. These high impedance current sources are capable of directly driving a

doubly terminated 75

Ω coaxial cable. All three current outputs should have similar output loads whether or not

they are all being used.

Sync current output. This high impedance current source can be directly connected to the IOG output. This al-

× V

Ω)

FS ADJUST

full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current.

is given by:

Ω) = 12,082 × V

IOR, IOB (mA) = 8,628

× V

Ω)

COMP

Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1

µF ceramic capacitor

Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. The use of an exter-

nal resistor divider network is not recommended. A 0.1

µF decoupling ceramic capacitor should be connected

Analog power supply (5 V

± 5%). All V

GND

Ground. All GND pins must be connected.