Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

ADT7316 Datasheet(PDF) 4 Page - Analog Devices

Part No. ADT7316
Description  SPI/I2C Compatible, 10-Bit Digital Temperature Sensor and Quad Voltage Output 12/10/8-Bit DAC
Download  32 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo 

ADT7316 Datasheet(HTML) 4 Page - Analog Devices

 
Zoom Inzoom in Zoom Outzoom out
 4 / 32 page
background image
–4–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
DAC AC CHARACTERISTICS1
(VDD = +2.7V to +5.5 V; RL=4k7Ω to GND; CL=200pF to GND;
4K7
Ω to V
DD; All specifications TMIN to TMAX unless otherwise noted.)
Parameter2
Min
Typ @ 25°C
M a x
Units
Conditions/Comments
Output Voltage Settling Time
VREF=VDD=+5V
ADT7318
6
8
µ s
1/4 Scale to 3/4 Scale change (40 Hex to C0 Hex)
ADT7317
7
9
µ s
1/4 Scale to 3/4 Scale change (100 Hex to 300 Hex)
ADT7316
8
1 0
µ s
1/4 Scale to 3/4 Scale change (400 Hex to
C00 Hex)
Slew Rate
0.7
V/µs
Major-Code Change Glitch Energy
1 2
nV-s
1 LSB change around major carry.
Digital Feedthrough
0.5
nV-s
Digital Crosstalk
1
nV-s
Analog Crosstalk
0.5
nV-s
DAC-to-DAC Crosstalk
3
nV-s
Multiplying Bandwidth
200
k H z
VREF=2V±0.1Vpp
Total Harmonic Distortion
-70
d B
VREF=2.5V±0.1Vpp. Frequency=10kHz.
NOTES
1Guaranteed by Design and Characterization, not production tested
2See Terminology
Specifications subject to change without notice.
t1
t4
t2
t
3
t5
SC L
SD A
DA T A IN
SD A
DA T A O U T
t6
Figure 1. Diagram for I2C Bus Timing
IDD (Normal Mode)
13
0.85
1.3
m A
VIH = VDD and VIL = GND
IDD (Power Down Mode)
1
3
µ A
VDD = +4.5V to +5.5V, VIH=VDD and VIL=GND
0.5
1
µ A
VDD = +2.7V to +3.6V, VIH=VDD and VIL=GND
Power Dissipation
tbd
tbd
tbd
µ W
VDD = +2.7 V. Using Normal Mode
tbd
tbd
tbd
µ W
VDD = +2.7 V. Using Shutdown Mode
Notes:
1 Temperature ranges are as follows: A Version: -40°C to +125°C.
2 See Terminology.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range:; ADT7316 (code 115 to 4095); ADT7317 (code 28 to 1023); ADT7318 (code 8 to 255)
5 See Terminology.
6 Guaranteed by Design and Characterization, not production tested
7 In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V
REF=VDD ,
"Offset plus Gain" Error must be positive.
8 The SDA & SCL timing is measured with the input filters turned on so as to meet the Fast-Mode I2C specification. Switching off the input filters improves the transfer
rate but has a negative affect on the EMC behaviour of the part.
9 Guaranteed by design. Not tested in production.
10 Guaranteed by design and characterization, not production tested.
11 All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of 1.6 V.
12 Measured with the load circuit of Figure 3.
13 I
DD spec. is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.
Specifications subject to change without notice.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn