Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

ADT7316 Datasheet(PDF) 3 Page - Analog Devices

Part No. ADT7316
Description  SPI/I2C Compatible, 10-Bit Digital Temperature Sensor and Quad Voltage Output 12/10/8-Bit DAC
Download  32 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo 

ADT7316 Datasheet(HTML) 3 Page - Analog Devices

 
Zoom Inzoom in Zoom Outzoom out
 3 / 32 page
background image
ADT7316/7317/7318
–3–
REV. PrN
PRELIMINARY TECHNICAL DATA
Scale Factor
2.2
mV/°C
0-VREF Output. TA = -40°C to +125°C
4.39
mV/°C
0-2VREF Output. TA = -40°C to +125°C
DAC ERTERNAL
REFERENCE INPUT
6
VREF Input Range
1
VDD
V
Buffered Reference Mode
VREF Input Range
0.25
VDD
V
Unbuffered Reference Mode
VREF Input Impedance
3 7
4 5
k
Unbuffered Reference Mode. 0-2 VREF Output Range.
74
90
k
Unbuffered Reference Mode. 0- VREF Output Range.
>10
M
Buffered reference mode and Power-Down Mode
Reference Feedthrough
-90
d B
Frequency=10KHz
Channel-toChannel Isolation
-75
d B
Frequency=10KHz
ON-CHIP REFERENCE
Reference Voltage6
2.25
V
Temperature Coefficient
6
8 0
ppm/
°C
OUTPUT CHARACTERISTICS
6
Output Voltage
7
0.001
VDD-0.001
V
This is a measure of the minimum and maximum drive
capability of the output amplifier
DC Output Impedance
0.5
Short Circuit Current
25
mA
VDD = +5V
16
m A
VDD = +3V
Power Up Time
2.5
µ s
Coming out of Power Down Mode. VDD = +5 V
5
µ s
Coming out of Power Down Mode. VDD = +3 V
DIGITAL INPUTS
6
Input Current
± 1
µ A
VIN = 0V to VDD
VIL, Input Low Voltage
0.8
V
VDD = +5V±10%
0.6
V
VDD = +3V±10%
VIH, Input High Voltage
1.89
V
Pin Capacitance
3
1 0
p F
All Digital Inputs
SCL, SDA Glitch Rejection
5 0
ns
Input Filtering Suppresses Noise Spikes of Less than 50
ns
DIGITAL OUTPUT
Output High Voltage, VOH
2.4
V
ISOURCE = ISINK = 200 µA
Output Low Voltage, VOL
0.4
V
IOL = 3 mA
Output High Current, IOH
1m A
VOH = 5 V
Output Capacitance, COUT
50
p F
ALERT Output Saturation Voltage
0.8
V
IOUT = 4 mA
I
2CTIMINGCHARACTERISTICS8,9
Serial Clock Period, t1
2.5
µ s
Fast-Mode I2C. See Figure 1
Data In Setup Time to SCL High, t2
Data Out Stable after SCL Low, t3
0
ns
See Figure 1
SDA Low Setup Time to SCL Low
(Start Condition), t4
50
ns
See Figure 1
SDA High Hold Time after SCL High
(Stop Condition), t5
50
ns
See Figure 1
SDA and SCL Fall Time, t6
90
ns
See Figure 1
SPI TIMING CHARACTERISTICS
10,11
CS to SCLK Setup Time, t
1
0
ns
See Figure 2
SCLK High Pulsewidth, t2
50
ns
See Figure 2
SCLK Low Pulse, t3
50
ns
See Figure 2
Data Access Time after
SCLK Falling edge, t4
12
35
ns
See Figure 2
Data Setup Time Prior
to SCLK Rising Edge, t5
20
ns
See Figure 2
Data Hold Time after
SCLK Rising Edge, t6
0
ns
See Figure 2
CS to SCLK Hold Time, t
7
0
ns
See Figure 2
CS to DOUT High Impedance, t
8
40
ns
See Figure 2
POWER REQUIREMENTS
VDD
2.7
5.5
V
VDD Settling Time
50
ms
VDD settles to within 10% of it’s final voltage
level.
Parameter
2
Min
Typ
M a x
Units
Conditions/Comments


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn