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ADSP-2187L Datasheet(PDF) 6 Page - Analog Devices
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ADSP-2187L Datasheet(HTML) 6 Page - Analog Devices
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The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are twelve levels deep to allow interrupt, loop and subroutine
nesting. The following instructions allow global enable or dis-
able servicing of the interrupts (including power down), regard-
less of the state of IMASK. Disabling the interrupts does not
affect serial port autobuffering or DMA.
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATION
The ADSP-2187L has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
The ADSP-2187L processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-down
features. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, “System Interface” chapter, for detailed information
about the power-down feature.
• Quick recovery from power-down. The processor begins ex-
ecuting instructions in as few as 400 CLKIN cycles.
• Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during power-
down without affecting the 400 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and let-
ting the oscillator run to allow 400 CLKIN cycle start up.
• Power-down is initiated by either the power-down pin (
or the software power-down force bit Interrupt support allows
an unlimited number of instructions to be executed before op-
tionally powering down. The power-down interrupt also can
be used as a non-maskable, edge-sensitive interrupt.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
RESET pin also can be used to terminate power- down.
• Power-down acknowledge pin indicates when the processor
has entered power-down.
When the ADSP-2187L is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then con-
tinues with the instruction following the IDLE instruction. In
Idle Mode IDMA, BDMA and autobuffer cycle steals still occur.
The IDLE instruction on the ADSP-2187L slows the processor’s
internal clock signal, further reducing power consumption. The
reduced clock frequency, a programmable fraction of the nor-
mal clock rate, is specified by a selectable divisor given in the
IDLE instruction. The format of the instruction is
where n = 16, 32, 64 or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2187L will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64
or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
Figure 2 shows a typical basic system configuration with the
ADSP-2187L, two serial devices, a byte-wide EPROM, and
optional external program and data overlay memories (mode se-
lectable). Programmable wait state generation allows the proces-
sor to connect easily to slow peripheral devices. The ADSP-2187L
also provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode al-
lows access to the full external data bus, but limits addressing to
a single address bit (A0) Additional system peripherals can be
added in this mode through the use of external hardware to gen-
erate and latch address signals.
The ADSP-2187L can be clocked by either a crystal or a TTL-
compatible clock signal.
The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed in-
formation on this power-down feature.
If an external clock is used, it should be a TTL-compatible sig-
nal running at half the instruction rate. The signal is connected
to the processor’s CLKIN input. When an external clock is
used, the XTAL input must be left unconnected.
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