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ADSP-2184L Datasheet(PDF) 3 Page - Analog Devices

Part No. ADSP-2184L
Description  DSP Microcomputer
Download  31 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com

ADSP-2184L Datasheet(HTML) 3 Page - Analog Devices

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REV. 0
The internal result (R) bus connects the computational units so
the output of any unit may be the input of any unit on the next
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2184L executes looped
code with zero overhead; no explicit jump instructions are re-
quired to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and pro-
gram memory. Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four pos-
sible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.
Efficient data transfer is achieved with the use of five internal
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-2184L to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2184L can fetch an operand from program memory and
the next instruction in the same cycle.
When configured in host mode, the ADSP-2184L has a 16-bit
Internal DMA port (IDMA port) for connection to external
systems. The IDMA port is made up of 16 data/address pins
and five control pins. The IDMA port provides transparent,
direct access to the DSPs on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with
programmable wait state generation. External devices can
gain control of external buses with bus request/grant signals
BR, BGH and BG). One execution mode (Go Mode) allows
the ADSP-2184L to continue running from on-chip memory.
Normal execution mode requires the processor to halt while
buses are granted.
The ADSP-2184L can respond to 13 interrupts. There are up to
six external interrupts (one edge-sensitive, two level-sensitive and
three configurable) and seven internal interrupts generated by
the timer, the serial ports (SPORTs), the Byte DMA port and
the power-down circuitry. There is also a master
RESET inter-
rupt. The two serial ports provide a complete synchronous serial
interface with optional companding in hardware and a wide
variety of framed or frameless data transmit and receive modes
of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSP-2184L provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs, and three flags are
always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) decrements every n processor
cycles, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-2184L incorporates two complete synchronous
serial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2184L SPORTs.
For additional information on Serial Ports, refer to the ADSP-
2100 Family User’s Manual, Third Edition.
• SPORTs are bidirectional and have a separate, double-buff-
ered transmit and receive section.
• SPORTs can use an external serial clock or generate their own
serial clock internally.
• SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and
µ-law companding according
to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.
• SPORT1 can be configured to have two external interrupts
IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
The ADSP-2184L is available in a 100-lead LQFP package. In
order to maintain maximum functionality and reduce package
size and pin count, some serial port, programmable flag, inter-
rupt and external bus pins have dual, multiplexed functionality.
The external bus pins are configured during
RESET only, while
serial port pins are software configurable during program execu-
tion. Flag and interrupt functionality is retained concurrently
on multiplexed pins. In cases where pin functionality is
reconfigurable, the default state is shown in plain text; alternate
functionality is shown in italics.

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