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ADSP-2104LKP-55 Datasheet(PDF) 8 Page - Analog Devices |
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ADSP-2104LKP-55 Datasheet(HTML) 8 Page - Analog Devices |
8 / 36 page ADSP-2104/ADSP-2109 –8– REV. 0 Boot Memory Interface Boot memory is an external 16K by 8 space, divided into eight separate 2K by 8 pages. The 8-bit bytes are automatically packed into 24-bit instruction words by the processor, for loading into on-chip program memory. Three bits in the processors’ System Control Register select which page is loaded by the boot memory interface. Another bit in the System Control Register allows the forcing of a boot loading sequence under software control. Boot loading from Page 0 after RESET is initiated automatically if MMAP = 0. The boot memory interface can generate zero to seven wait states; it defaults to three wait states after RESET. This allows the ADSP-2104 to boot from a single low cost EPROM such as a 27C256. Program memory is booted one byte at a time and converted to 24-bit program memory words. The BMS and RD signals are used to select and to strobe the boot memory interface. Only 8-bit data is read over the data bus, on pins D8-D15. To accommodate up to eight pages of boot memory, the two MSBs of the data bus are used in the boot memory interface as the two MSBs of the boot memory address: D23, D22, and A13 supply the boot page number. The ADSP-2100 Family Assembler and Linker allow the creation of programs and data structures requiring multiple boot pages during execution. The BR signal is recognized during the booting sequence. The bus is granted after loading the current byte is completed. BR during booting may be used to implement booting under control of a host processor. Bus Interface The ADSP-2104/ADSP-2109 can relinquish control of their data and address buses to an external device. When the external device requires control of the buses, it asserts the bus request signal (BR). If the processor is not performing an external memory access, it responds to the active BR input in the next cycle by: • Three-stating the data and address buses and the PMS, DMS , BMS, RD, WR output drivers, • Asserting the bus grant (BG) signal, • and halting program execution. If the Go mode is set, however, the ADSP-2104/ADSP-2109 will not halt program execution until it encounters an instruc- tion that requires an external memory access. If the processor is performing an external memory access when the external device asserts the BR signal, it will not three-state the memory interfaces or assert the BG signal until the cycle after the access completes (up to eight cycles later depending on the number of wait states). The instruction does not need to be completed when the bus is granted; the processor will grant the bus in between two memory accesses if an instruction requires more than one external memory access. When the BR signal is released, the processor releases the BG signal, re-enables the output drivers and continues program execution from the point where it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. If this feature is not used, the BR input should be tied high (to VDD). Low Power IDLE Instruction The IDLE instruction places the processor in low power state in which it waits for an interrupt. When an interrupt occurs, it is serviced and execution continues with instruction following IDLE. Typically this next instruction will be a JUMP back to the IDLE instruction. This implements a low-power standby loop. The IDLE n instruction is a special version of IDLE that slows the processor’s internal clock signal to further reduce power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor, n, given in the IDLE instruction. The syntax of the instruction is: IDLE n; where n = 16, 32, 64, or 128. The instruction leaves the chip in an idle state, operating at the slower rate. While it is in this state, the processor’s other internal clock signals, such as SCLK, CLKOUT, and the timer clock, are reduced by the same ratio. Upon receipt of an enabled interrupt, the processor will stay in the IDLE state for up to a maximum of n CLKIN cycles, where n is the divisor specified in the instruction, before resuming normal operation. When the IDLE n instruction is used, it slows the processor’s internal clock and thus its response time to incoming interrupts– the 1-cycle response time of the standard IDLE state is in- creased by n, the clock divisor. When an enabled interrupt is received, the ADSP-21xx will remain in the IDLE state for up to a maximum of n CLKIN cycles (where n = 16, 32, 64, or 128) before resuming normal operation. When the IDLE n instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the IDLE state (a maximum of n CLKIN cycles). |
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